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ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC)最新文献

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A 24-to-44 GHz Compact Linear 5G Power Amplifier with Open-Terminated Balun in 65nm Bulk CMOS 基于65nm CMOS的24- 44 GHz紧凑型线性5G功率放大器
ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2022-09-19 DOI: 10.1109/ESSCIRC55480.2022.9911289
Kyutaek Oh, Hyunjin Ahn, I. Nam, O. Lee
{"title":"A 24-to-44 GHz Compact Linear 5G Power Amplifier with Open-Terminated Balun in 65nm Bulk CMOS","authors":"Kyutaek Oh, Hyunjin Ahn, I. Nam, O. Lee","doi":"10.1109/ESSCIRC55480.2022.9911289","DOIUrl":"https://doi.org/10.1109/ESSCIRC55480.2022.9911289","url":null,"abstract":"This paper presents a broadband linear CMOS power amplifier (PA) for mm-wave 5G applications. A broadband low-loss open-terminated balun is proposed for a PA output network with a smaller size. The PA fabricated using a 65-nm bulk CMOS process shows flat saturated output power, Psat, ranging from 17.5 to 19.5 dBm, within 2-dB difference, while achieving over 24.5% peak PAE for CW signals ranging from 24 to 44 GHz. It achieves a flat linear output power, Plinear, of 10.4/11.6/10.9/8.8 dBm and a PlinearPAE, PAElinear, of 6.24/8.94/7.9/5.1% with -25-dB rms EVM, EVMrms, and -23.3/-25.7/-25.9/-22.8-dBc ACPR at 24/28/39/44 GHz. Using the 5G NR FR2 64-QAM 8-CC×100-MHz OFDM signal (PAPR = 9.7 dB), broadband operation was demonstrated over 24–44 GHz covering n257-261 5G bands. It has a core size of 0.15 mm2.","PeriodicalId":168466,"journal":{"name":"ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125272039","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A D-Band mm-wave spectroscopy TX and RX in 28 nm CMOS with 15.6 dBm EIRP and 17.1 dB NF with integrated antennas 在28 nm CMOS中，采用集成天线，采用15.6 dBm EIRP和17.1 dB NF，实现了d波段TX和RX的毫米波光谱
ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2022-09-19 DOI: 10.1109/ESSCIRC55480.2022.9911224
G. Guimaraes, P. Reynaert
{"title":"A D-Band mm-wave spectroscopy TX and RX in 28 nm CMOS with 15.6 dBm EIRP and 17.1 dB NF with integrated antennas","authors":"G. Guimaraes, P. Reynaert","doi":"10.1109/ESSCIRC55480.2022.9911224","DOIUrl":"https://doi.org/10.1109/ESSCIRC55480.2022.9911224","url":null,"abstract":"This paper presents a pair of CMOS D-band transmitter and receiver ICs to be used in mm-Wave spectroscopy systems. The TX consists of an on-chip VCO and divide chain for external frequency locking, a tripler, a power amplification chain and a power-combining on-chip antenna. It operates from 123 GHz to 142 GHz and has a peak EIRP of 15.6 dBm and 0.9 dBm of measured total radiated power (TRP). The heterodyne RX has an on-chip VCO and divide chain as well as an LNA, a passive mixer and a programmable IF amplifier. It operates at the same range as the TX. Its measured peak isotropic gain is 62.4 dB and isotropic noise figure is 3.1 dB at 134.7 GHz, which translate to a gain of 48.4 dB and NF of 17.1 dB when the antenna directivity is discounted. A spectroscopy system demonstration is built with the developed ICs and it is used to detect the 136.906 GHz absorption line of evaporated isopropyl alcohol.","PeriodicalId":168466,"journal":{"name":"ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114923306","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Mixed-Signal Compensation of Tripolar Cuff Electrode Imbalance in a Low-Noise ENG Analog Front-End 低噪声ENG模拟前端三极性袖口电极不平衡的混合信号补偿
ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2022-09-19 DOI: 10.1109/ESSCIRC55480.2022.9911326
R. Dekimpe, D. Bol
{"title":"Mixed-Signal Compensation of Tripolar Cuff Electrode Imbalance in a Low-Noise ENG Analog Front-End","authors":"R. Dekimpe, D. Bol","doi":"10.1109/ESSCIRC55480.2022.9911326","DOIUrl":"https://doi.org/10.1109/ESSCIRC55480.2022.9911326","url":null,"abstract":"Due to their low amplitude, electroneurogram (ENG) signals are particularly subject to external muscle artefacts and intrinsic electronic noise. However, achieving a high signal-to-noise ratio is a challenge for implanted systems that have a limited power budget. This work presents a low-power analog front-end which features low intrinsic noise and high interference rejection. The proposed mixed-signal feedback loop for tripolar cuff electrode imbalance compensation provides an interference rejection of 56 dB with a negligible power overhead. The instrumentation amplifier achieves a gain of 91.5 dB, an input-referred noise of 1.35 µV, an input offset voltage below 1 µV, and digitally-tunable imbalance compensation with 7 bits of resolution over a ±20 % range. The results are validated on the ICare microcontroller system-on-chip, a 22-nm fully-depleted silicon-on-insulator prototype.","PeriodicalId":168466,"journal":{"name":"ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115081508","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A 64Gb/s Downlink and 32Gb/s Uplink NRZ Wireline Transceiver with Supply Regulation, Background Clock Correction and EOM-based Channel Adaptation for Mid-Reach Cellular Mobile Interface in 8nm FinFET 用于8nm FinFET中程蜂窝移动接口的64Gb/s下行和32Gb/s上行NRZ有线收发器，具有电源调节、背景时钟校正和基于eom的信道自适应
ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2022-09-19 DOI: 10.1109/ESSCIRC55480.2022.9911419
Soo-Min Lee, Ji-Song Lim, Jaehyuk Jang, Hyoungjoon Kim, Kyunghwan Min, Woongki Min, Hyeonji Han, Gyusik Kim, Jaeyoung Kim, Chulho Kim, Sejun Jeon, Jinhoon Park, Hyunsu Chae, Sangwoo Han, H. Pham, Xingliang Zhao, Qilin Gu, Chih-Wei Yao, Sangho Kim, Jongwoo Lee
{"title":"A 64Gb/s Downlink and 32Gb/s Uplink NRZ Wireline Transceiver with Supply Regulation, Background Clock Correction and EOM-based Channel Adaptation for Mid-Reach Cellular Mobile Interface in 8nm FinFET","authors":"Soo-Min Lee, Ji-Song Lim, Jaehyuk Jang, Hyoungjoon Kim, Kyunghwan Min, Woongki Min, Hyeonji Han, Gyusik Kim, Jaeyoung Kim, Chulho Kim, Sejun Jeon, Jinhoon Park, Hyunsu Chae, Sangwoo Han, H. Pham, Xingliang Zhao, Qilin Gu, Chih-Wei Yao, Sangho Kim, Jongwoo Lee","doi":"10.1109/ESSCIRC55480.2022.9911419","DOIUrl":"https://doi.org/10.1109/ESSCIRC55480.2022.9911419","url":null,"abstract":"A 32Gb/s/lane NRZ wireline transceiver for the cellular mobile interface has been implemented. The maximum data bandwidth is 64Gb/s downlink and 32Gb/s uplink which meets the bandwidth requirement of the next FR2 standard. The master-slave LDO regulation is used to supply the stable power at each transmitter and receiver that operates independently. The dedicated clock correction and the channel adaptation have been performed to satisfy the time margin of 0.28UI at bit error rate (BER) of 10−12.","PeriodicalId":168466,"journal":{"name":"ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114339302","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A Drift-Compensated Magnetic Spectrometer for Point-of-Care Wash-Free Immunoassays using a Concurrent Dual-Frequency Oscillator 一个漂移补偿磁谱仪点护理免洗免疫测定使用并发双频振荡器
ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2022-09-19 DOI: 10.1109/ESSCIRC55480.2022.9911522
Jui-Hung Sun, Bill Ling, Md. Abdullah-Al Kaiser, Constantine Sideris
{"title":"A Drift-Compensated Magnetic Spectrometer for Point-of-Care Wash-Free Immunoassays using a Concurrent Dual-Frequency Oscillator","authors":"Jui-Hung Sun, Bill Ling, Md. Abdullah-Al Kaiser, Constantine Sideris","doi":"10.1109/ESSCIRC55480.2022.9911522","DOIUrl":"https://doi.org/10.1109/ESSCIRC55480.2022.9911522","url":null,"abstract":"A 2x2 magnetic spectrometer array using a concurrent dual-frequency transformer-based oscillator in 65nm CMOS is presented. Concurrent dual-frequency operation allows compensation of the drift of the free-running sensing oscillator without reconfiguring to switch the frequency of oscillation, which enables wash-free magnetic label assays and single-site multiplexed spectroscopy. The spectrometer achieves a sensitivity of 0.7ppm consuming only 3.1mW per cell over a wide frequency range of 1.2-1.65/2.9-4 GHz. A biotin-streptavidin immunoassay using iron oxide magnetic nanoparticle labels is performed without any washing steps, demonstrating high sensitivity and viability for point-of-care diagnostics.","PeriodicalId":168466,"journal":{"name":"ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134412947","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Coupling control in the few-electron regime of quantum dot arrays using 2-metal gate levels in CMOS technology 利用CMOS技术中的2金属栅极电平耦合控制量子点阵列的少电子态
ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2022-09-19 DOI: 10.1109/ESSCIRC55480.2022.9911381
B. C. Paz, Victor El-Homsy, D. Niegemann, B. Klemt, E. Chanrion, V. Thiney, B. Jadot, P. Mortemousque, B. Bertrand, T. Bedecarrats, H. Niebojewski, F. Perruchot, S. D. Franceschi, M. Vinet, M. Urdampilleta, T. Meunier
{"title":"Coupling control in the few-electron regime of quantum dot arrays using 2-metal gate levels in CMOS technology","authors":"B. C. Paz, Victor El-Homsy, D. Niegemann, B. Klemt, E. Chanrion, V. Thiney, B. Jadot, P. Mortemousque, B. Bertrand, T. Bedecarrats, H. Niebojewski, F. Perruchot, S. D. Franceschi, M. Vinet, M. Urdampilleta, T. Meunier","doi":"10.1109/ESSCIRC55480.2022.9911381","DOIUrl":"https://doi.org/10.1109/ESSCIRC55480.2022.9911381","url":null,"abstract":"Scalability is one of the biggest advantages of silicon spin qubits over other platforms, making them very promising candidates in the quest for quantum computing. In this work we approach the regime of interest for large-scale qubit integration, showing that we can deliver high electrostatic coupling control and individual tunability over an array of quantum dots (QDs). To do this we use FDSOI devices fabricated with 2-metal gate levels in an industry-compatible CMOS process. We operate them at 100mK, and in a dot-configuration where large control on tunnel barriers is leveraged. In the many-electron regime, we observe the transition of quantum dot array from single- to triple-dot configurations. Moreover, in the few-electron regime, we demonstrate the effective and in-situ modulation of the tunnel coupling between two adjacent QDs.","PeriodicalId":168466,"journal":{"name":"ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC)","volume":"379 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133910858","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Differentiable Neural Computer for Logic Reasoning with Scalable Near-Memory Computing and Sparsity Based Enhancement 基于可扩展近记忆计算和稀疏性增强的逻辑推理可微神经计算机
ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2022-09-19 DOI: 10.1109/ESSCIRC55480.2022.9911451
Yuhao Ju, Shiyu Guo, Zixuan Liu, Tianyu Jia, Jie Gu
{"title":"A Differentiable Neural Computer for Logic Reasoning with Scalable Near-Memory Computing and Sparsity Based Enhancement","authors":"Yuhao Ju, Shiyu Guo, Zixuan Liu, Tianyu Jia, Jie Gu","doi":"10.1109/ESSCIRC55480.2022.9911451","DOIUrl":"https://doi.org/10.1109/ESSCIRC55480.2022.9911451","url":null,"abstract":"Logic reasoning represents a new class of artificial intelligence. This work presents the first hardware implementation of the Differentiable Neural Computer accelerator based on brain inspired “working memory” concept for reasoning tasks. A special near-memory computing architecture is developed achieving high scalability and over 90% utilization of computing resources. Sparsity based enhancements such as zero skipping, data compression are applied with 30% speedup of the computing latency. A 65nm test chip was fabricated with demonstrations on a variety of logic reasoning tasks showing 700X and 46X speedup compared with CPU and GPU and up to 1.28TOPS/W power efficiency.","PeriodicalId":168466,"journal":{"name":"ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC)","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133258593","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Low-Power and Energy-Efficient D-Band CMOS Four-Channel Receiver with Integrated LO Generation for Digital Beamforming Arrays 一种用于数字波束形成阵列的低功耗、高能效d波段CMOS四通道接收器
ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2022-09-19 DOI: 10.1109/ESSCIRC55480.2022.9911448
Ethan Chou, Nima Baniasadi, Hesham Beshary, Meng Wei, Emily Naviasky, L. Iotti, A. Niknejad
{"title":"A Low-Power and Energy-Efficient D-Band CMOS Four-Channel Receiver with Integrated LO Generation for Digital Beamforming Arrays","authors":"Ethan Chou, Nima Baniasadi, Hesham Beshary, Meng Wei, Emily Naviasky, L. Iotti, A. Niknejad","doi":"10.1109/ESSCIRC55480.2022.9911448","DOIUrl":"https://doi.org/10.1109/ESSCIRC55480.2022.9911448","url":null,"abstract":"This work presents a $D$-band receiver characterized inside a four-channel transceiver with integrated local oscillator generation and distribution, intended for use in digital beamforming arrays. The receiver leverages a low-noise amplifier with an active balun to minimize its noise figure, while the local oscillator is optimized for low power consumption to enable scaling to larger arrays. A prototype implemented in 28-nm CMOS is flip-chip packaged onto an organic interposer with patch antenna arrays. A wireless downlink with the proposed receiver channel capable of supporting a data rate in excess of 12 Gb/s with QPSK and 16-QAM modulation, while achieving one of the lowest DC power consumption levels per element and energy-per-bit at 98 mW/element and 8.1 pJ/bit, respectively, demonstrates competitive performance and the highest level of integration compared to other $D$-band CMOS receiver wireless links.","PeriodicalId":168466,"journal":{"name":"ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128374585","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A 24V Thin-Film Ultrasonic Driver for Haptic Feedback in Metal-Oxide Thin-Film Technology using Hybrid DLL Locking Architecture 基于混合DLL锁定结构的金属氧化物薄膜触觉反馈24V薄膜超声驱动器
ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2022-09-19 DOI: 10.1109/ESSCIRC55480.2022.9911408
Jonas Pelgrims, K. Myny, W. Dehaene
{"title":"A 24V Thin-Film Ultrasonic Driver for Haptic Feedback in Metal-Oxide Thin-Film Technology using Hybrid DLL Locking Architecture","authors":"Jonas Pelgrims, K. Myny, W. Dehaene","doi":"10.1109/ESSCIRC55480.2022.9911408","DOIUrl":"https://doi.org/10.1109/ESSCIRC55480.2022.9911408","url":null,"abstract":"This paper presents a 24V high voltage (HV) ultrasonic driver for haptic feedback, designed to drive piezo-electric micromachined ultrasonic transducers (PMUT) using a unipolar 0.8um indium-galium-zinc-oxide (IGZO) thin-film transistor technology fabricated on a polymer substrate. A new hybrid DLL architecture is proposed to overcome the IGZO technology's shortcomings and leverage the accuracy and speed capabilities of Silicon technology. The ultrasonic driver is able to drive a transducer capacitance up to 36pF with a 4bit phase resolution and a frequency of 250kHz occupying a pitch matched area per pixel of $800mumathrm{m}times 800mu m$. This work presents the first fully integrated high-voltage ultrasonic driver in thin-film technology, further expanding the possible applications for thin-film technologies.","PeriodicalId":168466,"journal":{"name":"ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129361018","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 135 GHz 32 Gb/s Direct-Digital Modulation 16-QAM Transmitter in 28 nm CMOS 基于28nm CMOS的135ghz 32gb /s直接数字调制16-QAM发射机
ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2022-09-19 DOI: 10.1109/ESSCIRC55480.2022.9911352
Carl D’heer, P. Reynaert
{"title":"A 135 GHz 32 Gb/s Direct-Digital Modulation 16-QAM Transmitter in 28 nm CMOS","authors":"Carl D’heer, P. Reynaert","doi":"10.1109/ESSCIRC55480.2022.9911352","DOIUrl":"https://doi.org/10.1109/ESSCIRC55480.2022.9911352","url":null,"abstract":"This paper presents a 135 GHz direct-digital modulation 16-QAM transmitter employing a Cartesian architecture with separate phase and amplitude modulation. The transmitter, implemented in 28 nm CMOS, demonstrates a peak output power of 0 dBm. A maximum data rate of 32 Gb/$s$ is achieved using 16-QAM without any equalization or pulse shaping. Star-QAM and QPSK modulations lead to data rates of 27 Gb/$s$ and 24 Gb/$s$, respectively. The transmitter consumes 130 mW of DC power.","PeriodicalId":168466,"journal":{"name":"ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130118152","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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