ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC)最新文献_第2页

A Half-Bridge Gate-Driver for high-efficient Boost Converter Applications with single-sided ZVS and an adaptive Ringing Suppression Technique 一种用于单面ZVS和自适应振铃抑制技术的高效升压变换器的半桥栅驱动器

ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2022-09-19 DOI: 10.1109/ESSCIRC55480.2022.9911336

Michael Hanhart, Jonas Zoche, Jan Grobe, L. Weihs, Leo Rolff, R. Wunderlich, S. Heinen

引用次数: 0

A 28nm 1.644TFLOPS/W Floating-Point Computation SRAM Macro with Variable Precision for Deep Neural Network Inference and Training 用于深度神经网络推理和训练的28nm可变精度1.644TFLOPS/W浮点计算SRAM宏

ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2022-09-19 DOI: 10.1109/ESSCIRC55480.2022.9911450

Sangsu Jeong, Jeongwoo Park, Dongsuk Jeon

引用次数: 3

A 40nm RRAM Compute-in-Memory Macro with Parallelism-Preserving ECC for Iso-Accuracy Voltage Scaling 具有保持并行性ECC的40nm RRAM内存中计算宏用于等精度电压缩放

ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2022-09-19 DOI: 10.1109/ESSCIRC55480.2022.9911464

Wantong Li, James Read, Hongwu Jiang, Shimeng Yu

{"title":"A 40nm RRAM Compute-in-Memory Macro with Parallelism-Preserving ECC for Iso-Accuracy Voltage Scaling","authors":"Wantong Li, James Read, Hongwu Jiang, Shimeng Yu","doi":"10.1109/ESSCIRC55480.2022.9911464","DOIUrl":"https://doi.org/10.1109/ESSCIRC55480.2022.9911464","url":null,"abstract":"Compute-in-memory (CIM) employing resistive random access memory (RRAM) has been widely investigated as an attractive candidate to accelerate the heavy multiply-and-accumulate (MAC) workloads in deep neural networks (DNNs) inference. Supply voltage (VDD) scaling for compute engines is a popular technique to allow edge devices to toggle between high-performance and low-power modes. While prior CIM works have examined VDD scaling, they have not explored its effects on hardware errors and inference accuracy. In this work, we design and validate an RRAM-based CIM macro with a novel error correction code (ECC), called MAC-ECC, that can be reconfigured to correct errors arising from scaled VDD while preserving the parallelism of CIM. This enables RRAM-CIM to perform iso-accuracy inference across different operation modes. We design specialized hardware to implement the MAC-ECC decoder and insert it into the existing compute pipeline without throughput overhead. Additionally, we conduct measurements to characterize the effect of VDD scaling on errors in CIM. The macro is taped-out in TSMC N40 RRAM process, and for $1times 1b$ MAC operations on DenseNet-40 network it achieves 59.1 TOPS/W and 70.9 GOPS/mm2 at VDD of 0.7V, and 43.0 TOPS/W and 112.5 GOPS/mm2 at VDD of 1.0V. The design maintains <1% accuracy loss on the CIFAR-10 dataset across the tested VDDs.","PeriodicalId":168466,"journal":{"name":"ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126347442","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Switching Time Acceleration for High-Voltage CMOS RF Switch 高压CMOS射频开关的开关时间加速

ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2022-09-19 DOI: 10.1109/ESSCIRC55480.2022.9911368

Semen Syroiezhin, Oguzhan Oezdamar, R. Weigel, V. Solomko

引用次数: 1

A K-band Gilbert-Cell Frequency Doubler with Self-Adjusted 25% LO Duty-Cycle in SiGe BiCMOS Technology SiGe BiCMOS技术中自调25% LO占空比的k波段吉尔伯特单元倍频器

ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2022-09-19 DOI: 10.1109/ESSCIRC55480.2022.9911526

Lorenzo Piotto, Guglielmo De Filippi, D. D. Maistro, S. Erba, A. Mazzanti

{"title":"A K-band Gilbert-Cell Frequency Doubler with Self-Adjusted 25% LO Duty-Cycle in SiGe BiCMOS Technology","authors":"Lorenzo Piotto, Guglielmo De Filippi, D. D. Maistro, S. Erba, A. Mazzanti","doi":"10.1109/ESSCIRC55480.2022.9911526","DOIUrl":"https://doi.org/10.1109/ESSCIRC55480.2022.9911526","url":null,"abstract":"This paper presents a novel frequency doubler that further enhances the superior performance of solutions based on the Gilbert-cell mixer. A novel scheme is proposed to operate the cell with a 25 % LO duty-cycle. This technique boosts the conversion gain by generating a square-wave like output current. Moreover, the use of a quadrature generation block, commonly adopted in mixer-based frequency doublers, is not required, thus improving the operation bandwidth. The duty-cycle is automatically regulated by a low-frequency feedback loop which ensures optimal operation against input power and PVT variations. The performance of a test chip in a SiGe - BiCMOS process is presented. With a low supply voltage of 1.5 V, the chip achieves 6 dB conversion gain, 5.7 dBm peak $mathrm{P}_{text{sat}}$ and 17 % power efficiency at 20 G Hz. The doubler delivers $mathrm{P}_{text{sat}} > 3text{dB} mathrm{m}$ over more than one octave bandwidth. Experimental results compare favorably against previously reported frequency doublers in the same frequency range.","PeriodicalId":168466,"journal":{"name":"ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133812849","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Reconfigurable Digital Beamforming V-Band Phased-Array Receiver 一种可重构数字波束形成v波段相控阵接收机

ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2022-09-19 DOI: 10.1109/ESSCIRC55480.2022.9911486

Deniz Dosluoglu, Kun-Da Chu, Diego Peña-Colaiocco, Ivan Zhao, V. Sathe, J. Rudell

{"title":"A Reconfigurable Digital Beamforming V-Band Phased-Array Receiver","authors":"Deniz Dosluoglu, Kun-Da Chu, Diego Peña-Colaiocco, Ivan Zhao, V. Sathe, J. Rudell","doi":"10.1109/ESSCIRC55480.2022.9911486","DOIUrl":"https://doi.org/10.1109/ESSCIRC55480.2022.9911486","url":null,"abstract":"A scalable 4-element V-band digital beamforming phased-array receiver (RX) implemented in TSMC 28-nm CMOS integrates both an analog front-end and beamforming functions in the digital back-end (DBE). Each element includes a mixer-first front-end (MFFE), reconfigurable-resolution, oversampled in-phase and quadrature analog-to-digital converters (ADCs), adjustable finite impulse response (FIR) filters and beamforming weights applied at the DBE. The DBE can store pre- and post-beamforming data in a 0.5 Mb SRAM. The MFFE has an $mathrm{S}_{11}$ lower than -10 dB across an 8-GHz bandwidth centered around 52.5 GHz, a maximum gain of 27.1 dB and a minimum noise figure of 7.8 dB. The ADC has a maximum SNDR of 21 dB over a 100-MHz bandwidth when configured as a third-order continuous-time delta-sigma modulator. The chip was configured for experiments with low resolution (1-bit) ADCs which use a digitally-controlled dithering method to enhance the array gain. Although the RX only has 4 elements, the intent is to study the ability to recover information using low-resolution ADCs in a massively-arrayed front-end (FE) [1], [2]. Beamsteering at 0° and $45^{mathrm{o}}$ is demonstrated, and a maximum QPSK data rate of 400 MS/s with a minimum error vector magnitude (EVM) of -16.2 dB is achieved. The power and area consumption for one element including the FE, ADCs and custom digital interface is 96 mW and 0.18 mm2, respectively. The area for the entire system is 3.3 mm2.","PeriodicalId":168466,"journal":{"name":"ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC)","volume":"141 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115024061","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

A 32-ch Neuromodulator with redundant Voltage Monitors avoiding Blocking Capacitors 一种32-ch神经调制器，带有冗余电压监测器，避免阻塞电容器

ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2022-09-19 DOI: 10.1109/ESSCIRC55480.2022.9911370

Stefan Reich, Mark A. Sporer, J. Becker, Stefan B. Rieger, M. Schüttler, M. Ortmanns

{"title":"A 32-ch Neuromodulator with redundant Voltage Monitors avoiding Blocking Capacitors","authors":"Stefan Reich, Mark A. Sporer, J. Becker, Stefan B. Rieger, M. Schüttler, M. Ortmanns","doi":"10.1109/ESSCIRC55480.2022.9911370","DOIUrl":"https://doi.org/10.1109/ESSCIRC55480.2022.9911370","url":null,"abstract":"Neural recording and modulation has evolved rapidly in recent years. Closed-loop neuromodulation systems have been successfully demonstrated for the treatment of Parkinson's disease and epilepsy. Chronically implanted medical devices, requiring compliance to rigorous safety regulations, employ numerous safety measures to protect the patient. One such measure to prevent direct current from being applied to the tissue in case of a system failure is typically the usage of external blocking capacitors between the electrodes and the neuromodulator. These capacitors can cause significant magnetic resonance imaging (MRI) magnetic susceptibility artifacts that appear as a shading effect. This paper presents some of the challenges which arise when evolving neuromodulation hardware from benchtop prototypes to biomedical systems for chronic implantation in humans. We propose a novel safety measure to mitigate the MRI shading issue while still complying to the relevant safety regulations. Furthermore, we propose several additional features that improve the flexibility and usability of a 32-channel neuromodulation platform. The neuromodulator was fabricated in a 180 nm HV CMOS process and realizes a fully digital-to-neural interface.","PeriodicalId":168466,"journal":{"name":"ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115053862","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

A Full D-band Multi-Gbit RF-DAC in 90 nm SiGe BiCMOS based on Passive Vector Aggregation 基于被动矢量聚合的90nm SiGe BiCMOS全d波段多gbit / s RF-DAC

ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2022-09-19 DOI: 10.1109/ESSCIRC55480.2022.9911462

Tim Maiwald, A. Visweswaran, K. Aufinger, R. Weigel

{"title":"A Full D-band Multi-Gbit RF-DAC in 90 nm SiGe BiCMOS based on Passive Vector Aggregation","authors":"Tim Maiwald, A. Visweswaran, K. Aufinger, R. Weigel","doi":"10.1109/ESSCIRC55480.2022.9911462","DOIUrl":"https://doi.org/10.1109/ESSCIRC55480.2022.9911462","url":null,"abstract":"This paper presents the first fully integrated RF-DAC for realizing and passively scaling QPSK-signals for generating higher-order modulations over the entire D-band (110–170 GHz). Vector-symbol generation in the RF-DAC is accomplished via compact distributed passives on chip. In this modulator architecture, a sinusoidal local-oscillator (LO) signal is split and weighted by a backward-wave directional coupler to meet length requirements for a complex-valued RF-signal scaling vector. QPSK vector-modulation is then accomplished with a Lange Coupler, two Marchand baluns and a switch octet operating on four LO phases (0°, 90°, 180° and 270°), which is driven directly with the data streams. Higher-order modulation schemes are subsequently created by summing RF outputs of individual QPSK unit cells. A 16-QAM modulator, based on two-way summing, prototyped in Infineon's advanced 90 nm SiGe BiCMOS technology demonstrating a datarate of 6.4 Gbps with a measured EVM of <8% over the entire D-band. Simulations show a maximum datarate of 60 Gbps, however, the measured datarate is currently limited by the test setup comprising an in-house low-cost FPGA clocked at 1.6 GHz. The chip consumes 120 mW from a 2.1 V supply and occupies 0.36 mm2 of core area.","PeriodicalId":168466,"journal":{"name":"ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115789897","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Integrated Optical Phased Arrays on Silicon 硅基集成光学相控阵

ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2022-09-19 DOI: 10.1109/ESSCIRC55480.2022.9911229

F. Ashtiani, F. Aflatouni

引用次数: 0

A 385mV, 270nW, Accurate Voltage Level Detector for IoT 用于物联网的385mV, 270nW精确电压电平检测器

ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2022-09-19 DOI: 10.1109/ESSCIRC55480.2022.9911389

Omer Nechushtan, Asaf Feldman, J. Shor

引用次数: 0