Tim Maiwald, A. Visweswaran, K. Aufinger, R. Weigel
{"title":"基于被动矢量聚合的90nm SiGe BiCMOS全d波段多gbit / s RF-DAC","authors":"Tim Maiwald, A. Visweswaran, K. Aufinger, R. Weigel","doi":"10.1109/ESSCIRC55480.2022.9911462","DOIUrl":null,"url":null,"abstract":"This paper presents the first fully integrated RF-DAC for realizing and passively scaling QPSK-signals for generating higher-order modulations over the entire D-band (110–170 GHz). Vector-symbol generation in the RF-DAC is accomplished via compact distributed passives on chip. In this modulator architecture, a sinusoidal local-oscillator (LO) signal is split and weighted by a backward-wave directional coupler to meet length requirements for a complex-valued RF-signal scaling vector. QPSK vector-modulation is then accomplished with a Lange Coupler, two Marchand baluns and a switch octet operating on four LO phases (0°, 90°, 180° and 270°), which is driven directly with the data streams. Higher-order modulation schemes are subsequently created by summing RF outputs of individual QPSK unit cells. A 16-QAM modulator, based on two-way summing, prototyped in Infineon's advanced 90 nm SiGe BiCMOS technology demonstrating a datarate of 6.4 Gbps with a measured EVM of <8% over the entire D-band. Simulations show a maximum datarate of 60 Gbps, however, the measured datarate is currently limited by the test setup comprising an in-house low-cost FPGA clocked at 1.6 GHz. The chip consumes 120 mW from a 2.1 V supply and occupies 0.36 mm2 of core area.","PeriodicalId":168466,"journal":{"name":"ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2022-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"A Full D-band Multi-Gbit RF-DAC in 90 nm SiGe BiCMOS based on Passive Vector Aggregation\",\"authors\":\"Tim Maiwald, A. Visweswaran, K. Aufinger, R. Weigel\",\"doi\":\"10.1109/ESSCIRC55480.2022.9911462\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents the first fully integrated RF-DAC for realizing and passively scaling QPSK-signals for generating higher-order modulations over the entire D-band (110–170 GHz). Vector-symbol generation in the RF-DAC is accomplished via compact distributed passives on chip. In this modulator architecture, a sinusoidal local-oscillator (LO) signal is split and weighted by a backward-wave directional coupler to meet length requirements for a complex-valued RF-signal scaling vector. QPSK vector-modulation is then accomplished with a Lange Coupler, two Marchand baluns and a switch octet operating on four LO phases (0°, 90°, 180° and 270°), which is driven directly with the data streams. Higher-order modulation schemes are subsequently created by summing RF outputs of individual QPSK unit cells. A 16-QAM modulator, based on two-way summing, prototyped in Infineon's advanced 90 nm SiGe BiCMOS technology demonstrating a datarate of 6.4 Gbps with a measured EVM of <8% over the entire D-band. Simulations show a maximum datarate of 60 Gbps, however, the measured datarate is currently limited by the test setup comprising an in-house low-cost FPGA clocked at 1.6 GHz. The chip consumes 120 mW from a 2.1 V supply and occupies 0.36 mm2 of core area.\",\"PeriodicalId\":168466,\"journal\":{\"name\":\"ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC)\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2022-09-19\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ESSCIRC55480.2022.9911462\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSCIRC55480.2022.9911462","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A Full D-band Multi-Gbit RF-DAC in 90 nm SiGe BiCMOS based on Passive Vector Aggregation
This paper presents the first fully integrated RF-DAC for realizing and passively scaling QPSK-signals for generating higher-order modulations over the entire D-band (110–170 GHz). Vector-symbol generation in the RF-DAC is accomplished via compact distributed passives on chip. In this modulator architecture, a sinusoidal local-oscillator (LO) signal is split and weighted by a backward-wave directional coupler to meet length requirements for a complex-valued RF-signal scaling vector. QPSK vector-modulation is then accomplished with a Lange Coupler, two Marchand baluns and a switch octet operating on four LO phases (0°, 90°, 180° and 270°), which is driven directly with the data streams. Higher-order modulation schemes are subsequently created by summing RF outputs of individual QPSK unit cells. A 16-QAM modulator, based on two-way summing, prototyped in Infineon's advanced 90 nm SiGe BiCMOS technology demonstrating a datarate of 6.4 Gbps with a measured EVM of <8% over the entire D-band. Simulations show a maximum datarate of 60 Gbps, however, the measured datarate is currently limited by the test setup comprising an in-house low-cost FPGA clocked at 1.6 GHz. The chip consumes 120 mW from a 2.1 V supply and occupies 0.36 mm2 of core area.