A Full D-band Multi-Gbit RF-DAC in 90 nm SiGe BiCMOS based on Passive Vector Aggregation

Abstract

This paper presents the first fully integrated RF-DAC for realizing and passively scaling QPSK-signals for generating higher-order modulations over the entire D-band (110–170 GHz). Vector-symbol generation in the RF-DAC is accomplished via compact distributed passives on chip. In this modulator architecture, a sinusoidal local-oscillator (LO) signal is split and weighted by a backward-wave directional coupler to meet length requirements for a complex-valued RF-signal scaling vector. QPSK vector-modulation is then accomplished with a Lange Coupler, two Marchand baluns and a switch octet operating on four LO phases (0°, 90°, 180° and 270°), which is driven directly with the data streams. Higher-order modulation schemes are subsequently created by summing RF outputs of individual QPSK unit cells. A 16-QAM modulator, based on two-way summing, prototyped in Infineon's advanced 90 nm SiGe BiCMOS technology demonstrating a datarate of 6.4 Gbps with a measured EVM of <8% over the entire D-band. Simulations show a maximum datarate of 60 Gbps, however, the measured datarate is currently limited by the test setup comprising an in-house low-cost FPGA clocked at 1.6 GHz. The chip consumes 120 mW from a 2.1 V supply and occupies 0.36 mm2 of core area.