{"title":"用于深度神经网络推理和训练的28nm可变精度1.644TFLOPS/W浮点计算SRAM宏","authors":"Sangsu Jeong, Jeongwoo Park, Dongsuk Jeon","doi":"10.1109/ESSCIRC55480.2022.9911450","DOIUrl":null,"url":null,"abstract":"This paper presents a digital compute-in-memory (CIM) macro for accelerating deep neural networks. The macro provides high-precision computation required for training deep neural networks and running state-of-the-art models by supporting floating-point MAC operations. Additionally, the design supports variable computation precision, enabling optimized processing for different models and tasks. The design achieves 1.644TFLOPS/W energy efficiency and 57.9GFLOPS/mm2 computation density while supporting a wide range of floating-point data formats and computation precisions.","PeriodicalId":168466,"journal":{"name":"ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2022-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"A 28nm 1.644TFLOPS/W Floating-Point Computation SRAM Macro with Variable Precision for Deep Neural Network Inference and Training\",\"authors\":\"Sangsu Jeong, Jeongwoo Park, Dongsuk Jeon\",\"doi\":\"10.1109/ESSCIRC55480.2022.9911450\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a digital compute-in-memory (CIM) macro for accelerating deep neural networks. The macro provides high-precision computation required for training deep neural networks and running state-of-the-art models by supporting floating-point MAC operations. Additionally, the design supports variable computation precision, enabling optimized processing for different models and tasks. The design achieves 1.644TFLOPS/W energy efficiency and 57.9GFLOPS/mm2 computation density while supporting a wide range of floating-point data formats and computation precisions.\",\"PeriodicalId\":168466,\"journal\":{\"name\":\"ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC)\",\"volume\":\"37 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2022-09-19\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ESSCIRC55480.2022.9911450\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSCIRC55480.2022.9911450","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 28nm 1.644TFLOPS/W Floating-Point Computation SRAM Macro with Variable Precision for Deep Neural Network Inference and Training
This paper presents a digital compute-in-memory (CIM) macro for accelerating deep neural networks. The macro provides high-precision computation required for training deep neural networks and running state-of-the-art models by supporting floating-point MAC operations. Additionally, the design supports variable computation precision, enabling optimized processing for different models and tasks. The design achieves 1.644TFLOPS/W energy efficiency and 57.9GFLOPS/mm2 computation density while supporting a wide range of floating-point data formats and computation precisions.