A 12nm Agile-Designed SoC for Swarm-Based Perception with Heterogeneous IP Blocks, a Reconfigurable Memory Hierarchy, and an 800MHz Multi-Plane NoC

Tianyu Jia, Paolo Mantovani, Maico Cassel dos Santos, Davide Giri, Joseph Zuckerman, Erik Jens Loscalzo, M. Cochet, Karthik Swaminathan, Gabriele Tombesi, J. Zhang, Nandhini Chandramoorthy, J. Wellman, K. Tien, L. Carloni, Kenneth E. Shepard, D. Brooks, Gu-Yeon Wei, P. Bose
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引用次数: 9

Abstract

This paper presents an agile-designed domain-specific SoC in 12nm CMOS for the emerging application domain of swarm-based perception. Featuring a heterogeneous tile-based architecture, the SoC was designed with an agile methodology using open-source processors and accelerators, interconnected by a multi-plane NoC. A reconfigurable memory hierarchy and a CS-GALS clocking scheme allow the SoC to run at a variety of performance/power operating points. Compared to a high-end FPGA, the presented SoC achieves 7 × performance and 62× efficiency gains for the target application domain.
基于异构IP块、可重构内存结构和800MHz多平面NoC的12nm敏捷设计的基于群的感知SoC
针对基于群体感知的新兴应用领域,提出了一种基于12nm CMOS的敏捷设计的领域专用SoC。SoC采用基于异构瓷砖的架构,采用灵活的方法设计,使用开源处理器和加速器,通过多平面NoC相互连接。可重新配置的存储器层次结构和CS-GALS时钟方案允许SoC在各种性能/功率工作点上运行。与高端FPGA相比,该SoC在目标应用领域实现了7倍的性能提升和62倍的效率提升。
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