Tianyu Jia, Paolo Mantovani, Maico Cassel dos Santos, Davide Giri, Joseph Zuckerman, Erik Jens Loscalzo, M. Cochet, Karthik Swaminathan, Gabriele Tombesi, J. Zhang, Nandhini Chandramoorthy, J. Wellman, K. Tien, L. Carloni, Kenneth E. Shepard, D. Brooks, Gu-Yeon Wei, P. Bose
{"title":"A 12nm Agile-Designed SoC for Swarm-Based Perception with Heterogeneous IP Blocks, a Reconfigurable Memory Hierarchy, and an 800MHz Multi-Plane NoC","authors":"Tianyu Jia, Paolo Mantovani, Maico Cassel dos Santos, Davide Giri, Joseph Zuckerman, Erik Jens Loscalzo, M. Cochet, Karthik Swaminathan, Gabriele Tombesi, J. Zhang, Nandhini Chandramoorthy, J. Wellman, K. Tien, L. Carloni, Kenneth E. Shepard, D. Brooks, Gu-Yeon Wei, P. Bose","doi":"10.1109/ESSCIRC55480.2022.9911456","DOIUrl":null,"url":null,"abstract":"This paper presents an agile-designed domain-specific SoC in 12nm CMOS for the emerging application domain of swarm-based perception. Featuring a heterogeneous tile-based architecture, the SoC was designed with an agile methodology using open-source processors and accelerators, interconnected by a multi-plane NoC. A reconfigurable memory hierarchy and a CS-GALS clocking scheme allow the SoC to run at a variety of performance/power operating points. Compared to a high-end FPGA, the presented SoC achieves 7 × performance and 62× efficiency gains for the target application domain.","PeriodicalId":168466,"journal":{"name":"ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2022-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"9","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSCIRC55480.2022.9911456","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 9
Abstract
This paper presents an agile-designed domain-specific SoC in 12nm CMOS for the emerging application domain of swarm-based perception. Featuring a heterogeneous tile-based architecture, the SoC was designed with an agile methodology using open-source processors and accelerators, interconnected by a multi-plane NoC. A reconfigurable memory hierarchy and a CS-GALS clocking scheme allow the SoC to run at a variety of performance/power operating points. Compared to a high-end FPGA, the presented SoC achieves 7 × performance and 62× efficiency gains for the target application domain.