一个128ksps 120dB THD低噪声模拟前端

ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2022-09-19 DOI:10.1109/ESSCIRC55480.2022.9911425

Gerard Mora-Puchalt, Gabriel Banarie, Pawel Czapor, A. Sherry, R. Maurino, Jesús Bonache, Italo Medina

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引用次数: 0

摘要

本文介绍了一个完整的模数前端系统，该系统由一个可编程增益两级电容增益放大器(CGA)驱动一个多级delta-sigma ADC组成。它具有60kHz带宽和1ppm/FSR的低增益线性度($\mathrm{G}\leq 8$)和3ppm/FSR的高增益($\mathrm{G}> 8$)。在128的增益下，它在43mW的功耗下实现了5.5nV/√Hz的输入参考噪声。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A 128ksps 120dB THD Low Noise Analog Front End

This paper describes a complete analog to digital front-end system consisting of a programmable gain two stage capacitive gain amplifier (CGA) driving a multistage delta-sigma ADC. It features a 60kHz bandwidth and 1ppm/FSR linearity at low gains ($\mathrm{G}\leq 8$) and 3ppm/FSR at high gains ($\mathrm{G}> 8$). At a gain of 128, it achieves an input referred noise of 5.5nV/√Hz at a power consumption of 43mW.

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ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC)

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