Agata Iesurum, Davide Manente, F. Padovan, M. Bassi, A. Bevilacqua
{"title":"基于耦合锁相环的24ghz正交压控振荡器,相位噪声为-134 dBc/Hz,偏移量为10mhz","authors":"Agata Iesurum, Davide Manente, F. Padovan, M. Bassi, A. Bevilacqua","doi":"10.1109/ESSCIRC55480.2022.9911510","DOIUrl":null,"url":null,"abstract":"This work breaks the trade-off between quadrature error and phase noise, typical of quadrature voltage-controlled oscillators (QVCOs), by leveraging a coupled PLL approach. Prototypes implemented in a 28 nm bulk CMOS technology show $0.9^{\\circ}$ quadrature error, and -134 dBc/Hz phase noise at 10 MHz offset from the 24 GHz carrier. The measured tuning range spans from 24 to 29.2 GHz, while the power consumption is 60 mW.","PeriodicalId":168466,"journal":{"name":"ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2022-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"A 24 GHz Quadrature VCO Based on Coupled PLL with -134 dBc/Hz Phase Noise at 10 MHz Offset in 28 nm CMOS\",\"authors\":\"Agata Iesurum, Davide Manente, F. Padovan, M. Bassi, A. Bevilacqua\",\"doi\":\"10.1109/ESSCIRC55480.2022.9911510\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This work breaks the trade-off between quadrature error and phase noise, typical of quadrature voltage-controlled oscillators (QVCOs), by leveraging a coupled PLL approach. Prototypes implemented in a 28 nm bulk CMOS technology show $0.9^{\\\\circ}$ quadrature error, and -134 dBc/Hz phase noise at 10 MHz offset from the 24 GHz carrier. The measured tuning range spans from 24 to 29.2 GHz, while the power consumption is 60 mW.\",\"PeriodicalId\":168466,\"journal\":{\"name\":\"ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC)\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2022-09-19\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ESSCIRC55480.2022.9911510\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSCIRC55480.2022.9911510","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 24 GHz Quadrature VCO Based on Coupled PLL with -134 dBc/Hz Phase Noise at 10 MHz Offset in 28 nm CMOS
This work breaks the trade-off between quadrature error and phase noise, typical of quadrature voltage-controlled oscillators (QVCOs), by leveraging a coupled PLL approach. Prototypes implemented in a 28 nm bulk CMOS technology show $0.9^{\circ}$ quadrature error, and -134 dBc/Hz phase noise at 10 MHz offset from the 24 GHz carrier. The measured tuning range spans from 24 to 29.2 GHz, while the power consumption is 60 mW.