Configurable Energy-Efficient Lattice-Based Post-Quantum Cryptography Processor for IoT Devices

Abstract

This work presents a configurable lattice-based post-quantum cryptography processor suitable for lightweight edge devices. To reduce hardware cost and energy consumption, it employs a look-up-table-based modular multiplication for the number-theoretic transform and a real-time processing for polynomial sampling. Implementation in 28nm CMOS shows 15.4x and 14.5x reductions of gate count and on-chip memory size, respectively, compared to the previous state-of-the-art implementation at the cost of only 54% in energy.