{"title":"Non-Volatile Ternary Content Addressable Memory based on Phase Change Nanoelectromechanical (NEM) Relay","authors":"Mohammad Ayaz Masud, Luis Hurtado, G. Piazza","doi":"10.1109/ESSCIRC55480.2022.9911327","DOIUrl":null,"url":null,"abstract":"We demonstrate, for the first time, a ternary content-addressable memory (TCAM) architecture based on phase change nanoelectromechanical relays (PCNRs). The non-volatility (NV), high ON-OFF ratio (108), and low leakage operation make PCNR an ideal candidate for high density TCAM. Additionally, PCNR devices are back-end-of-the-line (BEOL) compatible, allowing for a very small TCAM cell size of 18F2. A TCAM, with only 1 transistor and 2 PCNR devices (1T2P) per cell is simulated and it exhibits 133 ps search latency and 0.721 pJ energy consumption for 64 bits, making it one of the most competitive approaches for TCAM using beyond CMOS technologies.","PeriodicalId":168466,"journal":{"name":"ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2022-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSCIRC55480.2022.9911327","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
We demonstrate, for the first time, a ternary content-addressable memory (TCAM) architecture based on phase change nanoelectromechanical relays (PCNRs). The non-volatility (NV), high ON-OFF ratio (108), and low leakage operation make PCNR an ideal candidate for high density TCAM. Additionally, PCNR devices are back-end-of-the-line (BEOL) compatible, allowing for a very small TCAM cell size of 18F2. A TCAM, with only 1 transistor and 2 PCNR devices (1T2P) per cell is simulated and it exhibits 133 ps search latency and 0.721 pJ energy consumption for 64 bits, making it one of the most competitive approaches for TCAM using beyond CMOS technologies.