A 1-to-4b 16.8-POPS/W 473-TOPS/mm2 6T-based In-Memory Computing SRAM in 22nm FD-SOI with Multi-Bit Analog Batch-Normalization

Abstract

Computing in-memory (CIM) is rapidly becoming an enticing solution to accelerate convolutional neural networks (CNNs) at the edge. Yet, low-precision current-based CIM-SRAMs face severe SNR degradation due to numerous analog non-idealities and high quantization noise when performing analog-to-digital conversion prior to digital batch-normalization (DBN). In this paper, we propose a dual-supply 1-to-4b CIM-SRAM macro in 22nm FD-SOI using 6T foundry bitcells, co-designed with a CIM-aware CNN training framework to overcome these challenges. The macro includes a multi-bit analog BN (ABN) unit combined with self-calibrating dual-phase sense-amplifiers (SCDP-SAs). Measurement results show peak 1b-normalized power and area efficiencies of 16.8POPS/W and 473TOPS/mm2at O.4/0.8V supply and 100 MHz, surpassing existing low-precision designs.