A 2.5 GHz 104 mW 57.35 dBc SFDR Non-linear DAC-based Direct-Digital Frequency Synthesizer in 65 nm CMOS Process

Abstract

This paper presents a direct-digital frequency synthesizer (DDS) with dynamic performance enhancement techniques. First, a fixed-weight decoder with an auxiliary DAC is proposed to remove the truncation spur of the phase accumulator. Second, the proposed tri-state decoding scheme reduces the number of current sources for reducing timing mismatches and capacitances. Finally, a fine current source reusing technique is developed to reduce the number of current sources and power consumption. The proposed DDS is fabricated in 65 nm CMOS technology. The worst SFDR is 57.35 dBc at 2.5 GHz with power consumption of 104 mW. The measured figure of merit is 18,124 GHz.2(SFDR/6)/W.