A 2.74pJ/conversion 0.0018mm2 Temperature Sensor with On-chip Gain and Offset Correction

This paper presents a dynamic temperature sensor in 65nm CMOS with on-chip analog gain and offset correction for low power systems. By shifting the reset phase of the N-bit ADC, offset correction with a range of $\pm 2^{(N-1)}$ LSB is realized. Fine tuning capacitors are introduced to improve the offset correction accuracy to 0.5LSB. By adding programmable parasitic capacitors, gain errors up to 6.3% can be compensated. Thanks to the proposed analog correction techniques, the gain errors are reduced to 0.73% and the offsets are reduced to 0.5LSB. This sensor consumes 2.74pJ per conversion and only occupies an area of 0.0018 mm2 including the extra correction techniques. It has an RMS resolution of 0.47K, leading to a FoM of 0.6 pJ.K2.