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2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD)最新文献

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Extending the RET-IGBT (recessed emitter trench IGBT) concept to high voltages: Experimental demonstration of 3.3kV RET IGBT 将RET-IGBT(嵌入式发射极沟槽IGBT)概念扩展到高压:3.3kV RET-IGBT的实验演示
2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2018-05-13 DOI: 10.1109/ISPSD.2018.8393622
L. Ngwendson, I. Deviny, C. Zhu, I. Saddiqui, C. Kong, A. Islam, J. Hutchings, J. Thompson, M. Briggs, O. Basset, H. Luo, Y. Wang, Y. Yao
{"title":"Extending the RET-IGBT (recessed emitter trench IGBT) concept to high voltages: Experimental demonstration of 3.3kV RET IGBT","authors":"L. Ngwendson, I. Deviny, C. Zhu, I. Saddiqui, C. Kong, A. Islam, J. Hutchings, J. Thompson, M. Briggs, O. Basset, H. Luo, Y. Wang, Y. Yao","doi":"10.1109/ISPSD.2018.8393622","DOIUrl":"https://doi.org/10.1109/ISPSD.2018.8393622","url":null,"abstract":"In this paper we show simulation and experimental results of new 3.3kV RET-IGBT (Recessed Emitter Trench IGBT). Simulation results show that although the RET concept reduces the active region's trench to trench mesa, it does not show the reported inversion layer modulation phenomenon in conventional \"narrow mesa\" devices, which can degrade performance with very fine dimensions. It is also shown that High Voltage RET-IGBT can show superior VCE(sat) performance compared to standard Trench IGBT without degrading the dynamic performance such as RBSOA and SCSOA when devices are paralleled.","PeriodicalId":166809,"journal":{"name":"2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"105 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126309774","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Enhancement of punch-through voltage in GaN with buried p-type layer utilizing polarization-induced doping 利用极化诱导掺杂提高埋p型氮化镓的穿通电压
2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2018-05-13 DOI: 10.1109/ISPSD.2018.8393644
Wenshen Li, M. Zhu, K. Nomoto, Zongyang Hu, Xiang Gao, M. Pilla, D. Jena, H. Xing
{"title":"Enhancement of punch-through voltage in GaN with buried p-type layer utilizing polarization-induced doping","authors":"Wenshen Li, M. Zhu, K. Nomoto, Zongyang Hu, Xiang Gao, M. Pilla, D. Jena, H. Xing","doi":"10.1109/ISPSD.2018.8393644","DOIUrl":"https://doi.org/10.1109/ISPSD.2018.8393644","url":null,"abstract":"The effect of polarization induced (Pl)-doping in GaN buried p-type layer on reverse blocking is studied for the first time. Forward and reverse I-V characteristics is measured on n-p-n diodes. With PI-doping in the buried p-type layer, the reverse punch-through voltage increases from 30 V to 240 V, even with hydrogen passivating the Mg acceptors, indicating the unique advantage of PI-doping on reverse blocking. The enhanced punch-through voltage is attributed to the polarization fixed charge in the p-layer, which is extracted to be ∼1.3×1017 cm−3 and closely matched with the expected value of 1.4×1017 cm−3. Vertical trench-MOSFETs with a breakdown voltage of 225 V are also demonstrated on the same sample.","PeriodicalId":166809,"journal":{"name":"2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116077747","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Performance and reliability insights of drain extended FinFET devices for high voltage SoC applications 用于高压SoC应用的漏极扩展FinFET器件的性能和可靠性见解
2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2018-05-13 DOI: 10.1109/ISPSD.2018.8393605
B. Kumar, Milova Paul, M. Shrivastava, H. Gossner
{"title":"Performance and reliability insights of drain extended FinFET devices for high voltage SoC applications","authors":"B. Kumar, Milova Paul, M. Shrivastava, H. Gossner","doi":"10.1109/ISPSD.2018.8393605","DOIUrl":"https://doi.org/10.1109/ISPSD.2018.8393605","url":null,"abstract":"In this paper1, Drain extended FinFET device design and the challenges associated with the performance and reliability are discussed. Physical insights into the performance vs. reliability trade-off for the Fin enabled high voltage designs is elaborated and compared with their planar counterpart (DeMOS). Effect of Fin width discretization over ESD reliability, Safe Operating Area and HCI reliability are discussed.","PeriodicalId":166809,"journal":{"name":"2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129271811","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Dynamic performance analysis of a 3.3 kV SiC MOSFET half-bridge module with parallel chips and body-diode freewheeling 3.3 kV体二极管并联MOSFET半桥模块动态性能分析
2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2018-05-13 DOI: 10.1109/ISPSD.2018.8393703
A. Hussein, B. Mouawad, A. Castellazzi
{"title":"Dynamic performance analysis of a 3.3 kV SiC MOSFET half-bridge module with parallel chips and body-diode freewheeling","authors":"A. Hussein, B. Mouawad, A. Castellazzi","doi":"10.1109/ISPSD.2018.8393703","DOIUrl":"https://doi.org/10.1109/ISPSD.2018.8393703","url":null,"abstract":"Recently, 3.3 and 6.5 kV power MOSFETs have been introduced. Based on the 3.3 kV device, a 100 A half-bridge power module has been developed, using parallel chips for current scaling and relying exclusively on the use of the transistors body-diode for current free-wheeling (i.e., no antiparallel external diode chips are used). This paper presents a thorough parametric characterization of the module switching performance. Single-chip and parallel-chip operation are investigated in both double-pulsea type tests and realistic singlephase inverter operation.","PeriodicalId":166809,"journal":{"name":"2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131562818","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Local lifetime control for enhanced ruggedness of HVDC thyristors 增强高压直流晶闸管坚固性的局部寿命控制
2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2018-05-13 DOI: 10.1109/ISPSD.2018.8393626
J. Vobecký, V. Boţan, K. Meier, K. Tugan, M. Bellini
{"title":"Local lifetime control for enhanced ruggedness of HVDC thyristors","authors":"J. Vobecký, V. Boţan, K. Meier, K. Tugan, M. Bellini","doi":"10.1109/ISPSD.2018.8393626","DOIUrl":"https://doi.org/10.1109/ISPSD.2018.8393626","url":null,"abstract":"Proton irradiation is experimentally demonstrated to increase the ruggedness of large area thyristors for HVDC. While maintaining very low On-state losses at V<inf>T</inf> below 1.7 V and 1.8 V for 7.2 and 8.5 kV classes (I<inf>T</inf> = 6.25 kA, T = 90 °C), record low leakage current has been achieved at 150 mm silicon wafers together with increased surge current, higher dV/dt capability and lower circuit commutated recovery time t<inf>q</inf>.","PeriodicalId":166809,"journal":{"name":"2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114431159","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
P-gate GaN HEMT gate-driver design for joint optimization of switching performance, freewheeling conduction and short-circuit robustness p栅极GaN HEMT栅极驱动器设计，结合开关性能、自由导通和短路鲁棒性优化
2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2018-05-13 DOI: 10.1109/ISPSD.2018.8393645
Han Wu, A. Fayyaz, A. Castellazzi
{"title":"P-gate GaN HEMT gate-driver design for joint optimization of switching performance, freewheeling conduction and short-circuit robustness","authors":"Han Wu, A. Fayyaz, A. Castellazzi","doi":"10.1109/ISPSD.2018.8393645","DOIUrl":"https://doi.org/10.1109/ISPSD.2018.8393645","url":null,"abstract":"This paper proposes the design and prototype development and testing of a gate-driver which enables to jointly optimize the performance in application of gate-injection type high electron mobility transistors, taking into account a number of diverse operational conditions, including nominal and abnormal events. The results show that it is possible to optimize the gate-driver parameters in such a way as to ensure optimum switching and free-wheeling performance, while ensuring enhanced short-circuit robustness.","PeriodicalId":166809,"journal":{"name":"2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114726443","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Si wafer technology for power devices: A review and future directions 功率器件用硅片技术综述及未来发展方向
2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2018-05-13 DOI: 10.1109/ISPSD.2018.8393591
N. Machida
{"title":"Si wafer technology for power devices: A review and future directions","authors":"N. Machida","doi":"10.1109/ISPSD.2018.8393591","DOIUrl":"https://doi.org/10.1109/ISPSD.2018.8393591","url":null,"abstract":"Silicon wafers have been widely used in semiconductor devices for years. Their characteristics have been improved by untiring development efforts to meet power device manufacturers' requirements such as lowering substrate resistivity for Power MOSFET and reducing resistivity variation for IGBT. As future directions, by utilizing advantages of silicon wafers, adoption of MCZ grown bulk silicon wafers for low and middle voltage IGBT and introduction of 300mm size silicon wafers will proceed.","PeriodicalId":166809,"journal":{"name":"2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122531616","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Breakthrough of drain current capability and on-resistance limits by gate-connected superjunction MOSFET 栅极连接超结MOSFET突破漏极电流能力和导通电阻限制
2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2018-05-13 DOI: 10.1109/ISPSD.2018.8393596
W. Saito
{"title":"Breakthrough of drain current capability and on-resistance limits by gate-connected superjunction MOSFET","authors":"W. Saito","doi":"10.1109/ISPSD.2018.8393596","DOIUrl":"https://doi.org/10.1109/ISPSD.2018.8393596","url":null,"abstract":"This paper reports a new structure of Gate-connected Superjunction (GS) MOSFET to cope with both high drain current density and low on-resistance. The conventional superjunction (SJ) structure is attractive to reduce the specific on-resistance dramatically due to the charge compensation concept. The drain saturation current density, however, is limited by JFET depletion at the bottom region of the SJ structure even if the on-resistance can be reduced by the lateral SJ pitch narrowing. The accumulation-mode operation is effective not only for low on-resistance but also for suppressing the depletion at the SJ bottom due to the accumulation carriers. This paper reports the potential of the GS-MOSFET for high drain current density and low on-resistance based on the simulation results. Dynamic characteristics are also compared with the conventional SJ-MOSFET.","PeriodicalId":166809,"journal":{"name":"2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115631486","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Coss losses in silicon superjunction MOSFETs across constructions and generations 硅超结mosfet的结构和世代损耗
2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2018-05-13 DOI: 10.1109/ISPSD.2018.8393621
G. Zulauf, J. Rivas-Davila
{"title":"Coss losses in silicon superjunction MOSFETs across constructions and generations","authors":"G. Zulauf, J. Rivas-Davila","doi":"10.1109/ISPSD.2018.8393621","DOIUrl":"https://doi.org/10.1109/ISPSD.2018.8393621","url":null,"abstract":"The superjunction (SJ) structure breaks the unipolar material limit of silicon power MOSFETs, and has achieved widespread adoption in commercial power converters. In resonant applications, these SJ devices experience losses due to charging and discharging the parasitic output capacitor, Coss, resulting in losses that increase with switching frequency. We document COSS losses in commercially-available 600 V superjunction devices, showing that even devices grown with the trench-filling epitaxial method have non-negligible losses in MHz converters. Further, progressing in generations within a manufacturer appears to correspond to higher COSS losses as the cell pitch is reduced and doping is increased. The COSS losses may exceed conduction losses in many applications for the devices tested here.","PeriodicalId":166809,"journal":{"name":"2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"2017 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127571182","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
1 kV/1.3 mΩ·cm2 vertical GaN-on-GaN Schottky barrier diodes with high switching performance 1 kV/1.3 mΩ·cm2垂直GaN-on-GaN肖特基势垒二极管，具有高开关性能
2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2018-05-13 DOI: 10.1109/ISPSD.2018.8393655
Shu Yang, Shaowen Han, Rui Li, Kuang Sheng
{"title":"1 kV/1.3 mΩ·cm2 vertical GaN-on-GaN Schottky barrier diodes with high switching performance","authors":"Shu Yang, Shaowen Han, Rui Li, Kuang Sheng","doi":"10.1109/ISPSD.2018.8393655","DOIUrl":"https://doi.org/10.1109/ISPSD.2018.8393655","url":null,"abstract":"In this paper, we present vertical GaN Schottky barrier diodes implemented on bulk GaN substrates, delivering a breakdown voltage of ∼1 kV, a specific ON-resistance of 1.3 mΩ·cm2 with current spreading considered, a high current swing over 13 orders of magnitude and a low ideality factor of 1.04. The developed devices exhibit current-collapse-free operation under 400 V/500 ns switching condition as well as zero reverse recovery characteristics, showing great potential for high-power and high-frequency applications.","PeriodicalId":166809,"journal":{"name":"2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132534760","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
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