2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD)最新文献

CMOS bi-directional ultra-wideband galvanically isolated die-to-die communication utilizing a double-isolated transformer 利用双隔离变压器的CMOS双向超宽带电隔离模对模通信

2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2018-06-22 DOI: 10.1109/ISPSD.2018.8393609

M. Javid, K. Ptáček, R. Burton, J. Kitchen

{"title":"CMOS bi-directional ultra-wideband galvanically isolated die-to-die communication utilizing a double-isolated transformer","authors":"M. Javid, K. Ptáček, R. Burton, J. Kitchen","doi":"10.1109/ISPSD.2018.8393609","DOIUrl":"https://doi.org/10.1109/ISPSD.2018.8393609","url":null,"abstract":"In this work, an ultra-wideband (UWB) bi-directional galvanic isolator (BDGI) is reported for the first time. The proposed design methodology uses time-division-duplex (TDD) protocol to merge the functionality of two passive galvanically isolated channels into one magnetically coupled communication channel between two chips, enabling up to 50% form-factor and assembly cost reduction while achieving state-of-art performance. A low-power UWB pulse polarity-modulated transceiver architecture is presented to maximize the channel's capacity to 300 Mb/s and minimize power consumption and propagation delay to 200 pj/b and 5 ns respectively. The communication channel utilizes a double-isolated transformer coupled channel consisting of two transformers connected in series using bondwires and achieves 11 kVpk (7.8 kVrms) high voltage isolation, the highest reported without adding extra steps or alternating the native CMOS fabrication process. The system is realized in a 0.25 um BCD (Bipolar-CMOS-DMOS) process with 0.8 mm2 silicon area per channel. The system uses odd-symmetry center-tapped transformers and differential transceivers to increase noise/transient immunity.","PeriodicalId":166809,"journal":{"name":"2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"111 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115850546","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

A more accurate electromagnetic modeling of WBG power modules 更精确的WBG电源模块电磁建模

2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2018-05-13 DOI: 10.1109/ISPSD.2018.8393652

Ivana Kovačević-Badstübner, U. Grossner, D. Romano, G. Antonini, J. Ekman

{"title":"A more accurate electromagnetic modeling of WBG power modules","authors":"Ivana Kovačević-Badstübner, U. Grossner, D. Romano, G. Antonini, J. Ekman","doi":"10.1109/ISPSD.2018.8393652","DOIUrl":"https://doi.org/10.1109/ISPSD.2018.8393652","url":null,"abstract":"A major requirement for further development of wide-band gap (WBG) power devices and their applications is the optimization of packages and PCB layouts to enable fast-switching capabilities. Electromagnetic modelling allows the prediction of parasitic inductances, capacitances, and resistances of the current paths within power modules, which cannot be easily approached in measurements. As a result, electromagnetic-circuit-coupled modeling enables the optimization of package layouts and interconnections before manufacturing actual power modules. The accuracy and limitations of present numerical techniques for three-dimensional (3D) electromagnetic modeling of power modules is still neither well understood nor verified. This paper presents the extraction of parasitics of power semiconductor packages using two electromagnetic modelling approaches. The first approach is based on a well-established 3D electromagnetic quasi-static solver, ANSYS Q3D Extractor. For the second approach, a numerical solver based on the Partial Element Equivalent Circuit (PEEC) method is developed and assessed in terms of modelling accuracy required by fast switching WBG-based power converters. The PEEC method is presented as a promising numerical technique, which can potentially be used to overcome the limitations of the EM modeling based on the ANSYS Q3D Extractor.","PeriodicalId":166809,"journal":{"name":"2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115628932","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

Investigation of threshold voltage stability of SiC MOSFETs SiC mosfet阈值电压稳定性研究

2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2018-05-13 DOI: 10.1109/ISPSD.2018.8393597

D. Peters, T. Aichinger, T. Basler, G. Rescher, K. Puschkarsky, H. Reisinger

引用次数: 52

Sn- and Cu-oxide reduction by formic acid and its application to power module soldering 甲酸还原锡、铜氧化物及其在电源模块焊接中的应用

2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2018-05-13 DOI: 10.1109/ISPSD.2018.8393649

Naoto Ozawa, T. Okubo, J. Matsuda, T. Sakai

引用次数: 2

Gate architecture design for enhancement mode p-GaN gate HEMTs for 200 and 650V applications 用于200和650V应用的增强模式p-GaN栅极hemt的栅极架构设计

2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2018-05-13 DOI: 10.1109/ISPSD.2018.8393634

N. Posthuma, S. You, S. Stoffels, H. Liang, M. Zhao, S. Decoutere

引用次数: 23

Uni-directional GaN-on-Si MOSHEMTs with high reverse-blocking voltage based on nanostructured Schottky drain 基于纳米结构肖特基漏极的单向高反向阻断电压GaN-on-Si MOSHEMTs

2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2018-05-13 DOI: 10.1109/ISPSD.2018.8393635

Jun Ma, E. Matioli

引用次数: 2

Investigation on single pulse avalanche failure of 900V SiC MOSFETs 900V SiC mosfet单脉冲雪崩失效研究

2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2018-05-13 DOI: 10.1109/ISPSD.2018.8393695

Na Ren, Hao Hu, Kang L. Wang, Zheng Zuo, Ruigang Li, Kuang Sheng

引用次数: 12

Reduction of RonA retaining high threshold voltage in SiC DioMOS by improved channel design 通过改进通道设计降低SiC DioMOS中RonA保持高阈值电压

2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2018-05-13 DOI: 10.1109/ISPSD.2018.8393600

A. Ohoka, M. Uchida, T. Kiyosawa, N. Horikawa, K. Saitou, Y. Kanzawa, H. Sorada, K. Sawada, T. Ueda

引用次数: 4

Chip-scale cooling of power semiconductor devices: Fabrication of Jet impingement design 功率半导体器件的芯片级冷却:射流冲击设计的制造

2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2018-05-13 DOI: 10.1109/ISPSD.2018.8393716

Feng Zhou, K. Jung, Y. Fukuoka, E. Dede

{"title":"Chip-scale cooling of power semiconductor devices: Fabrication of Jet impingement design","authors":"Feng Zhou, K. Jung, Y. Fukuoka, E. Dede","doi":"10.1109/ISPSD.2018.8393716","DOIUrl":"https://doi.org/10.1109/ISPSD.2018.8393716","url":null,"abstract":"Chip-scale cooling is proposed for future wide bandgap (WBG) power semiconductor devices to overcome challenges associated with device power dissipation, high heat fluxes up to 1 kW/cm2, and traditional package thermal resistance. In the current paper, fabrication of a chip-scale cooler that utilizes fluid jet impingement plus flow through an optimized branching microchannel topology is described. This chip-scale cooling structure is expected to provide an estimated 70% higher cooling performance for the same pumping power and more uniform cooling relative to a straight microchannel design based on prior numerical and experimental studies. The proposed embedded flow structure is defined by three layers, and each layer is fabricated by double-sided etching of a six-inch silicon wafer. The final device is obtained by bonding the three etched layers together and dicing the three-wafer stack into individual chips. The design and fabrication of the cooling chip, including process challenges and solutions, is the focus of the current paper. Discussion of the current technology and a vision of its future application is also provided.","PeriodicalId":166809,"journal":{"name":"2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128248836","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

High-temperature validated SiC power MOSFET model for flexible robustness analysis of multi-chip structures 用于多芯片结构柔性鲁棒性分析的高温验证SiC功率MOSFET模型

2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2018-05-13 DOI: 10.1109/ISPSD.2018.8393698

M. Riccio, V. d’Alessandro, G. Romano, L. Maresca, G. Breglio, A. Irace, A. Castellazzi

引用次数: 5