A. Ohoka, M. Uchida, T. Kiyosawa, N. Horikawa, K. Saitou, Y. Kanzawa, H. Sorada, K. Sawada, T. Ueda
{"title":"Reduction of RonA retaining high threshold voltage in SiC DioMOS by improved channel design","authors":"A. Ohoka, M. Uchida, T. Kiyosawa, N. Horikawa, K. Saitou, Y. Kanzawa, H. Sorada, K. Sawada, T. Ueda","doi":"10.1109/ISPSD.2018.8393600","DOIUrl":null,"url":null,"abstract":"Trade-off between threshold voltage and specific on-resistance is successfully overcome in a diode-integrated SiC MOSFET by improving the design of n-type epitaxial channel layer and p-type body region. This new design features enhanced transconductance, hence low on-state resistance, while retaining high threshold voltage. Obtained specific on-resistance of the fabricated 1200V SiC DioMOS is among the lowest achieved for SiC MOSFETs including trench devices. The transconductance enhancement is also demonstrated to be effective in increasing the turn-on switching speed, thus contributing to higher efficiency in power switching systems with reduced conduction and switching losses.","PeriodicalId":166809,"journal":{"name":"2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISPSD.2018.8393600","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4
Abstract
Trade-off between threshold voltage and specific on-resistance is successfully overcome in a diode-integrated SiC MOSFET by improving the design of n-type epitaxial channel layer and p-type body region. This new design features enhanced transconductance, hence low on-state resistance, while retaining high threshold voltage. Obtained specific on-resistance of the fabricated 1200V SiC DioMOS is among the lowest achieved for SiC MOSFETs including trench devices. The transconductance enhancement is also demonstrated to be effective in increasing the turn-on switching speed, thus contributing to higher efficiency in power switching systems with reduced conduction and switching losses.
通过改进n型外延沟道层和p型体区的设计,成功地克服了阈值电压和特定导通电阻之间的权衡。这种新设计具有增强的跨导性,因此具有低导通电阻,同时保持高阈值电压。所获得的1200V SiC DioMOS的导通电阻是SiC mosfet(包括沟槽器件)中最低的。跨导增强在提高导通开关速度方面也被证明是有效的,从而有助于提高功率开关系统的效率,降低导通和开关损耗。