{"title":"利用双隔离变压器的CMOS双向超宽带电隔离模对模通信","authors":"M. Javid, K. Ptáček, R. Burton, J. Kitchen","doi":"10.1109/ISPSD.2018.8393609","DOIUrl":null,"url":null,"abstract":"In this work, an ultra-wideband (UWB) bi-directional galvanic isolator (BDGI) is reported for the first time. The proposed design methodology uses time-division-duplex (TDD) protocol to merge the functionality of two passive galvanically isolated channels into one magnetically coupled communication channel between two chips, enabling up to 50% form-factor and assembly cost reduction while achieving state-of-art performance. A low-power UWB pulse polarity-modulated transceiver architecture is presented to maximize the channel's capacity to 300 Mb/s and minimize power consumption and propagation delay to 200 pj/b and 5 ns respectively. The communication channel utilizes a double-isolated transformer coupled channel consisting of two transformers connected in series using bondwires and achieves 11 kVpk (7.8 kVrms) high voltage isolation, the highest reported without adding extra steps or alternating the native CMOS fabrication process. The system is realized in a 0.25 um BCD (Bipolar-CMOS-DMOS) process with 0.8 mm2 silicon area per channel. The system uses odd-symmetry center-tapped transformers and differential transceivers to increase noise/transient immunity.","PeriodicalId":166809,"journal":{"name":"2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"111 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":"{\"title\":\"CMOS bi-directional ultra-wideband galvanically isolated die-to-die communication utilizing a double-isolated transformer\",\"authors\":\"M. Javid, K. Ptáček, R. Burton, J. Kitchen\",\"doi\":\"10.1109/ISPSD.2018.8393609\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this work, an ultra-wideband (UWB) bi-directional galvanic isolator (BDGI) is reported for the first time. The proposed design methodology uses time-division-duplex (TDD) protocol to merge the functionality of two passive galvanically isolated channels into one magnetically coupled communication channel between two chips, enabling up to 50% form-factor and assembly cost reduction while achieving state-of-art performance. A low-power UWB pulse polarity-modulated transceiver architecture is presented to maximize the channel's capacity to 300 Mb/s and minimize power consumption and propagation delay to 200 pj/b and 5 ns respectively. The communication channel utilizes a double-isolated transformer coupled channel consisting of two transformers connected in series using bondwires and achieves 11 kVpk (7.8 kVrms) high voltage isolation, the highest reported without adding extra steps or alternating the native CMOS fabrication process. The system is realized in a 0.25 um BCD (Bipolar-CMOS-DMOS) process with 0.8 mm2 silicon area per channel. The system uses odd-symmetry center-tapped transformers and differential transceivers to increase noise/transient immunity.\",\"PeriodicalId\":166809,\"journal\":{\"name\":\"2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD)\",\"volume\":\"111 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2018-06-22\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"6\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISPSD.2018.8393609\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISPSD.2018.8393609","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
CMOS bi-directional ultra-wideband galvanically isolated die-to-die communication utilizing a double-isolated transformer
In this work, an ultra-wideband (UWB) bi-directional galvanic isolator (BDGI) is reported for the first time. The proposed design methodology uses time-division-duplex (TDD) protocol to merge the functionality of two passive galvanically isolated channels into one magnetically coupled communication channel between two chips, enabling up to 50% form-factor and assembly cost reduction while achieving state-of-art performance. A low-power UWB pulse polarity-modulated transceiver architecture is presented to maximize the channel's capacity to 300 Mb/s and minimize power consumption and propagation delay to 200 pj/b and 5 ns respectively. The communication channel utilizes a double-isolated transformer coupled channel consisting of two transformers connected in series using bondwires and achieves 11 kVpk (7.8 kVrms) high voltage isolation, the highest reported without adding extra steps or alternating the native CMOS fabrication process. The system is realized in a 0.25 um BCD (Bipolar-CMOS-DMOS) process with 0.8 mm2 silicon area per channel. The system uses odd-symmetry center-tapped transformers and differential transceivers to increase noise/transient immunity.