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2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD)最新文献

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A novel divided STI-based nLDMOSFET for suppressing HCI degradation under high gate bias stress 一种在高栅极偏置应力下抑制HCI退化的新型分栅基nLDMOSFET
2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2018-05-01 DOI: 10.1109/ISPSD.2018.8393662
T. Mori, Shunji Kubo, T. Ipposhi
{"title":"A novel divided STI-based nLDMOSFET for suppressing HCI degradation under high gate bias stress","authors":"T. Mori, Shunji Kubo, T. Ipposhi","doi":"10.1109/ISPSD.2018.8393662","DOIUrl":"https://doi.org/10.1109/ISPSD.2018.8393662","url":null,"abstract":"Incorporating a P-type REduced SURface Field (RESURF) layer under an N-type drift region in an nLDMOSFET is a well-known means of improving the trade-off between the on-resistance (Rsp) and off-state breakdown voltage (BVoff), as well as reducing hot carrier injection (HCI) degradation. However, the N-type buffer layer under the drain N+ region must be eliminated to maintain a high BVoff in such structures. Generally, HCI degradation occurs near the channelside STI edge at the maximum substrate current (Isubmax). In addition, new HCI degradation occurs in the vicinity of the drain-side STI edge under high gate bias and drain bias conditions because a high electric field is generated near this region. Herein, a new nLDMOSFET in which the STI is divided near the drain-side edge is proposed to suppress this HCI degradation while maintaining the Rsp-Bvoff trade-off.","PeriodicalId":166809,"journal":{"name":"2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127947676","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Power cycling reliability results of GaN HEMT devices GaN HEMT器件的功率循环可靠性结果
2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2018-05-01 DOI: 10.1109/ISPSD.2018.8393704
J. Franke, Guang Zeng, Tom Winkler, J. Lutz
{"title":"Power cycling reliability results of GaN HEMT devices","authors":"J. Franke, Guang Zeng, Tom Winkler, J. Lutz","doi":"10.1109/ISPSD.2018.8393704","DOIUrl":"https://doi.org/10.1109/ISPSD.2018.8393704","url":null,"abstract":"The GaN HEMT is a novel wide bandgap device which could improve the overall efficiency and at the same time shrink the system size. In order to verify the reliability of this promising semiconductor device, new measurement and testing methods have to be developed. In this work, as a general basis for performing reliability tests junction temperature measurement methods for GaN HEMT were investigated. By using suitable temperature measurement method, several power cycling tests were performed on GaN HEMT from three different manufacturers. The main failure mechanism of the GaN HEMT from two manufacturers under power cycling tests is the degradation of solder layer between device and printed circuit board. The main failure mechanism of the devices from the third manufacturer is bond wire lift-off. In GaN the piezoelectric effect is involved in the formation of the 2DEG, and electrical characteristics are sensitive to compressive and tensile stress. The question is whether repetitive deformation leads to new failure mechanisms compared to Si devices.","PeriodicalId":166809,"journal":{"name":"2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124446568","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 34
Surge capability of 1.2kV SiC diodes with high-temperature implantation 高温注入1.2kV SiC二极管的浪涌性能
2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2018-05-01 DOI: 10.1109/ISPSD.2018.8393692
Hongyi Xu, Jiahui Sun, J. Cui, Jiupeng Wu, Hengyu Wang, Shu Yang, Na Ren, Kuang Sheng
{"title":"Surge capability of 1.2kV SiC diodes with high-temperature implantation","authors":"Hongyi Xu, Jiahui Sun, J. Cui, Jiupeng Wu, Hengyu Wang, Shu Yang, Na Ren, Kuang Sheng","doi":"10.1109/ISPSD.2018.8393692","DOIUrl":"https://doi.org/10.1109/ISPSD.2018.8393692","url":null,"abstract":"This paper presents a high-temperature implanted 4H-SiC JBS diode with improved surge capability. The fabrication of the P+ region is implemented with 500 °C implantation. It was found that Ti can form ohmic contact on high temperature implanted P+ region without any additional annealing. This could simplify the ohmic contact process for MPS fabrication. In this work, a wide transition P+ region between cell and termination is designed, which can alleviate snapback phenomenon and improve the surge capability.","PeriodicalId":166809,"journal":{"name":"2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126601830","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Normally-OFF dual-gate Ga2O3 planar MOSFET and FinFET with high ION and BV 常关双栅Ga2O3平面MOSFET和FinFET具有高离子和BV
2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2018-05-01 DOI: 10.1109/ISPSD.2018.8393682
H. Wong, N. Braga, R. Mickevicius, F. Ding
{"title":"Normally-OFF dual-gate Ga2O3 planar MOSFET and FinFET with high ION and BV","authors":"H. Wong, N. Braga, R. Mickevicius, F. Ding","doi":"10.1109/ISPSD.2018.8393682","DOIUrl":"https://doi.org/10.1109/ISPSD.2018.8393682","url":null,"abstract":"Ga<inf>2</inf>O<inf>3</inf> is a promising Wide-Band-Gap material for power electronics due to its large bandgap and inexpensive native substrate. However, due to technological difficulties, only normally-ON n-type junctionless MOSFET (V<inf>th</inf> < 0 V) can be made easily. We propose using dual-gate configuration to achieve normally-OFF device for both Ga<inf>2</inf>O<inf>3</inf> planar MOSFET and FinFET. Through TCAD simulations with calibrated parameters, it is found that normally-OFF dual-gate planar device and FinFET can be achieved with 6X and 1X enhancement in ON-current (I<inf>ON</inf>), respectively, as higher doping is allowed, while breakdown voltage is not sacrificed.","PeriodicalId":166809,"journal":{"name":"2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133535173","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Investigation of the mechanism of gate voltage oscillation in 1.2kV IGBT under short circuit condition 短路条件下1.2kV IGBT栅电压振荡机理研究
2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2018-05-01 DOI: 10.1109/ISPSD.2018.8393713
Takuo Kikuchi, K. Nakamura, K. Takao
{"title":"Investigation of the mechanism of gate voltage oscillation in 1.2kV IGBT under short circuit condition","authors":"Takuo Kikuchi, K. Nakamura, K. Takao","doi":"10.1109/ISPSD.2018.8393713","DOIUrl":"https://doi.org/10.1109/ISPSD.2018.8393713","url":null,"abstract":"The mechanism of the gate oscillation under short circuit condition was studied by experiment and simulation. In the both ways, dependence of input DC-link voltage Vcc and stray inductance Le on the gate oscillation was examined to clarify the cause. It has been found that under short circuit a high electric field formed in the collector side and hole transit time delay plays a critical role for the onset of oscillation. Based on the model, its parametric dependence can be clearly interpreted. In addition, the design to suppress the oscillation has been discussed.","PeriodicalId":166809,"journal":{"name":"2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132662216","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Integrated symmetrical high-voltage inverter for the excitation of touch sensitive electroluminescent devices 用于触敏电致发光器件励磁的一体化对称高压逆变器
2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2018-05-01 DOI: 10.1109/ISPSD.2018.8393673
Katrin Hirmer, M. Saif, K. Hofmann
{"title":"Integrated symmetrical high-voltage inverter for the excitation of touch sensitive electroluminescent devices","authors":"Katrin Hirmer, M. Saif, K. Hofmann","doi":"10.1109/ISPSD.2018.8393673","DOIUrl":"https://doi.org/10.1109/ISPSD.2018.8393673","url":null,"abstract":"Smart Power Integrated Circuits are commonly used where different operating voltages are required since it can enable miniaturization of the system electronics. For the combination of an electroluminescent device with a capacitive touch sensor, a μm SOI integrated circuit is implemented with a high-voltage inverter and a low-voltage spread spectrum clock generator. The transient signals with up to ± 300 Vp and 5 kHz show interferences on the digital sensor excitation signal.","PeriodicalId":166809,"journal":{"name":"2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"1994 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130415801","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A split gate vertical GaN power transistor with intrinsic reverse conduction capability and low gate charge 一种具有本征反导能力和低栅极电荷的分栅垂直GaN功率晶体管
2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2018-05-01 DOI: 10.1109/ISPSD.2018.8393640
R. Zhu, Qi Zhou, H. Tao, Yi Yang, Kai Hu, D. Wei, Liyang Zhu, Yuanyuan Shi, Wanjun Chen, X. Luo, Bo Zhang
{"title":"A split gate vertical GaN power transistor with intrinsic reverse conduction capability and low gate charge","authors":"R. Zhu, Qi Zhou, H. Tao, Yi Yang, Kai Hu, D. Wei, Liyang Zhu, Yuanyuan Shi, Wanjun Chen, X. Luo, Bo Zhang","doi":"10.1109/ISPSD.2018.8393640","DOIUrl":"https://doi.org/10.1109/ISPSD.2018.8393640","url":null,"abstract":"In this work, a vertical normally-off GaN device featuring split-gate with intrinsic reverse conduction (RCVFET) functionality and low gate capacitance is proposed and studied by simulation. Different from the lateral AlGaN/GaN HEMT, the RC characteristics of the proposed RCVFET are independent with the threshold voltage of the device, while a low VR, ON of 0.8 V is obtained. Owing to the split-gate design, the gate charge is respectably reduced that is beneficial for improving the switching speed of the RCVFET. The device exhibits a low Ron of 0.93 mΩ.cm2 and a BV of 1280V. The reverse recovery time is 13ns. The QGD is 80 nC that is only one fifth of that obtained in the reference device without split-gate.","PeriodicalId":166809,"journal":{"name":"2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116132246","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Evaluation of gate oxide reliability in 3.3 kV 4H-SiC DMOSFET with J-Ramp TDDB methods 用J-Ramp TDDB方法评价3.3 kV 4H-SiC DMOSFET栅氧化可靠性
2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2018-05-01 DOI: 10.1109/ISPSD.2018.8393678
M. Sagawa, H. Miki, Y. Mori, H. Shimizu, A. Shima
{"title":"Evaluation of gate oxide reliability in 3.3 kV 4H-SiC DMOSFET with J-Ramp TDDB methods","authors":"M. Sagawa, H. Miki, Y. Mori, H. Shimizu, A. Shima","doi":"10.1109/ISPSD.2018.8393678","DOIUrl":"https://doi.org/10.1109/ISPSD.2018.8393678","url":null,"abstract":"In order to verify a gate oxide reliability of 3.3 kV 4H-SiC DMOS for rail car application, we developed a J-Ramp TDDB and a constant current stress screening method. We examined a conventional gate stack structure device with a single layer gate electrode and an improved one with double layered gate electrode; the latter one reveals a low hazard rate less than 1 FIT under a gate operation voltage of ±15 V at 150 °C.","PeriodicalId":166809,"journal":{"name":"2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122605786","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A balancing method for low Ron and high Vth normally-off GaN MISFET by preserving a damage-free thin AlGaN barrier layer 一种通过保留无损伤的薄AlGaN势垒层来平衡低Ron和高Vth正常关断GaN MISFET的方法
2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2018-05-01 DOI: 10.1109/ISPSD.2018.8393643
Jialin Zhang, Liang He, Liuan Li, Y. Ni, Taotao Que, Zhenxing Liu, Wenjing Wang, Jiexin Zheng, Yanfen Huang, J. Chen, Xin Gu, Yawen Zhao, Lei He, Zhisheng Wu, Yang Liu
{"title":"A balancing method for low Ron and high Vth normally-off GaN MISFET by preserving a damage-free thin AlGaN barrier layer","authors":"Jialin Zhang, Liang He, Liuan Li, Y. Ni, Taotao Que, Zhenxing Liu, Wenjing Wang, Jiexin Zheng, Yanfen Huang, J. Chen, Xin Gu, Yawen Zhao, Lei He, Zhisheng Wu, Yang Liu","doi":"10.1109/ISPSD.2018.8393643","DOIUrl":"https://doi.org/10.1109/ISPSD.2018.8393643","url":null,"abstract":"Partially AlGaN recessed scheme based on selective area growth was experimentally demonstrated to improve the performance of normally-off GaN MISFET. The damage-free thin AlGaN barrier layer with lower Al-content in recessed region contributes to a positive Vth shift compared with the reference one (from 1.8 V to 2.5 V). At the same time this method realizes a high peak μκΣ of 2033 cm2/V·s and a low gate channel sheet resistance of 519 Ω/□ (@Vg = 12 V), which is a significant improvement compared with the fully recessed-gate device. The higher Al-contents AlGaN barrier layer regrown in accessed region is adopted to maintain high-conductivity 2DEG transport property. As a result, a maximum drain current of 645 mA/mm and a low on-resistance of 6.8 Ω-mni are obtained. The GaN MISFET also exhibits a low hysteresis, low gate leakage and slight current collapse. This technique could fabricate very promising normally-off GaN devices by designing thickness and Al-content of the controllable-growth thin AlGaN barrier layer.","PeriodicalId":166809,"journal":{"name":"2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125141468","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A high-speed SOI-LIGBT with electric potential modulation trench and low-doped buried layer 一种具有电势调制沟槽和低掺杂埋层的高速soi - light
2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2018-05-01 DOI: 10.1109/ISPSD.2018.8393668
Shaohong Li, Long Zhang, Jing Zhu, Weifeng Sun, Qingxi Tang, Hao Wang, Ling Sun, Yan Gu, Shikang Cheng, Sen Zhang, Y. Yi
{"title":"A high-speed SOI-LIGBT with electric potential modulation trench and low-doped buried layer","authors":"Shaohong Li, Long Zhang, Jing Zhu, Weifeng Sun, Qingxi Tang, Hao Wang, Ling Sun, Yan Gu, Shikang Cheng, Sen Zhang, Y. Yi","doi":"10.1109/ISPSD.2018.8393668","DOIUrl":"https://doi.org/10.1109/ISPSD.2018.8393668","url":null,"abstract":"A high-voltage SOI-LIGBT with high turn-off speed and low turn-off loss (EOFF) is proposed in this paper. The proposed SOI-LIGBT features a Low-doped Buried N-layer (LBN) region and an emitter-side Electric Potential Modulation Trench (EPMT) shorted with the P+ emitter. By employing the LBN and EPMT, fast extraction of the stored carrier and the high turn-off speed are realized due to the accelerated depletion of N-drift region. The simulated results show that the proposed SOI-LIGBT can achieve a 73% lower turn-off loss compared with the conventional SOI-LIGBT at the same VON of 1.52V. Moreover, the hole heat flux distribution in the proposed device predicts an improvement of ruggedness under high-voltage and high-current conditions.","PeriodicalId":166809,"journal":{"name":"2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127537515","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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