用J-Ramp TDDB方法评价3.3 kV 4H-SiC DMOSFET栅氧化可靠性

2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2018-05-01 DOI:10.1109/ISPSD.2018.8393678

M. Sagawa, H. Miki, Y. Mori, H. Shimizu, A. Shima

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引用次数: 8

摘要

为了验证3.3 kV 4H-SiC DMOS用于轨道车辆的栅氧化可靠性，我们开发了J-Ramp TDDB和恒流应力筛选方法。研究了传统的单层栅极叠层结构器件和改进的双层栅极叠层结构器件;后者显示出在150°C下±15 V栅极工作电压下小于1 FIT的低危险率。

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Evaluation of gate oxide reliability in 3.3 kV 4H-SiC DMOSFET with J-Ramp TDDB methods

In order to verify a gate oxide reliability of 3.3 kV 4H-SiC DMOS for rail car application, we developed a J-Ramp TDDB and a constant current stress screening method. We examined a conventional gate stack structure device with a single layer gate electrode and an improved one with double layered gate electrode; the latter one reveals a low hazard rate less than 1 FIT under a gate operation voltage of ±15 V at 150 °C.

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来源期刊

2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD)

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