发布求助
文献互助 智能选刊 最新文献

2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD)最新文献

筛选
英文 中文
Novel 3D narrow mesa IGBT suppressing CIBL 新型3D窄台IGBT抑制CIBL
2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2018-05-01 DOI: 10.1109/ISPSD.2018.8393618
Masahiro Tanaka, A. Nakagawa
{"title":"Novel 3D narrow mesa IGBT suppressing CIBL","authors":"Masahiro Tanaka, A. Nakagawa","doi":"10.1109/ISPSD.2018.8393618","DOIUrl":"https://doi.org/10.1109/ISPSD.2018.8393618","url":null,"abstract":"It was reported that the experimentally fabricated very narrow mesa IGBT has poor short-circuit withstand capability because of CIBL. We propose a novel narrow mesa IGBT, which suppresses CIBL. Additional deep P+ diffusion layer inside the P-base improves CIBL by reducing the enhanced conductivity modulation in the channel inversion layer. The structure achieves good short-circuit withstand capability and superior trade-off relationship between on-state voltage drop and turn-off loss.","PeriodicalId":166809,"journal":{"name":"2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133647950","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Reverse-blocking AlGaN/GaN normally-off MIS-HEMT with double-recessed gated Schottky drain 具有双凹槽门控肖特基漏极的反向阻断AlGaN/GaN正常关闭miss - hemt
2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2018-05-01 DOI: 10.1109/ISPSD.2018.8393656
Jiacheng Lei, Jin Wei, Gaofei Tang, K. J. Chen
{"title":"Reverse-blocking AlGaN/GaN normally-off MIS-HEMT with double-recessed gated Schottky drain","authors":"Jiacheng Lei, Jin Wei, Gaofei Tang, K. J. Chen","doi":"10.1109/ISPSD.2018.8393656","DOIUrl":"https://doi.org/10.1109/ISPSD.2018.8393656","url":null,"abstract":"A reverse blocking AlGaN/GaN normally-Off MIS-HEMT featuring double-recessed gated Schottky drain was demonstrated on a double-channel HEMT platform. Two recess steps with robust recess depth tolerance are performed to form the MIS-gated Schottky drain. The shallow recess stops at the upper GaN channel layer where a MIS-gated section (i.e. MIS field plate) is formed to suppress the reverse leakage current. The deep recess cuts through the lower 2DEG channel where a metal-2DEG Schottky contact with low turn-on voltage is formed along the sidewall. Since the lower channel is separated from the surface of the shallow recess, the MIS-gated section in the drain maintains a high mobility channel to yield a sheet resistance of 806 Ω/Square. The device exhibits a threshold voltage of +0.6 V at a drain leakage current of 10 μΑ/mm and +1.9 V from linear extrapolation, and a low differential ON-resistance of ∼11 Ω/mm. Owing to the presence of the metal-2DEG Schottky contact and the leakage-suppression MIS field plate in the drain, a low forward turn-on voltage of 0.5 V and a low reverse leakage current of 20 nA/mm (at −100 V) are achieved simultaneously. The device also exhibits a high forward and reverse breakdown voltage of 700 V and −600 V.","PeriodicalId":166809,"journal":{"name":"2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"153 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133143608","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Reliability investigation with accelerated body diode current stress for 3.3 kV 4H-SiC MOSFETs with various buffer epilayer thickness 3.3 kV不同缓冲层厚度4H-SiC mosfet的加速体二极管电流应力可靠性研究
2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2018-05-01 DOI: 10.1109/ISPSD.2018.8393699
Y. Ebiike, Takeshi Murakami, E. Suekawa, Shigehisa Yamamoto, H. Sumitani, M. Imaizumi, M. Tarutani
{"title":"Reliability investigation with accelerated body diode current stress for 3.3 kV 4H-SiC MOSFETs with various buffer epilayer thickness","authors":"Y. Ebiike, Takeshi Murakami, E. Suekawa, Shigehisa Yamamoto, H. Sumitani, M. Imaizumi, M. Tarutani","doi":"10.1109/ISPSD.2018.8393699","DOIUrl":"https://doi.org/10.1109/ISPSD.2018.8393699","url":null,"abstract":"3.3 kV 4H-SiC MOSFETs with various buffer layer thickness has been fabricated in order to investigate the bipolar degradation associated with the expansion of stacking faults (SFs). The body diode stress tests under DC current of 240 A/cm2 were performed at 200 °C. Shifts in specific on-resistance (Ron, sp) and forward voltage (Vf) of body diode were markedly reduced for the MOSFETs with thick buffer layer of 30 μm. This result indicates that the body diode reliability may be improved by suitably designed buffer layer. The photoluminescence (PL) image of these SiC epilayer after the stress tests revealed the SF expansion due to the bipolar current stress was suppressed by the thick buffer layer.","PeriodicalId":166809,"journal":{"name":"2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121971076","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Repetitive surge current test of SiC MPS diode with load in bipolar regime 负载双极状态下SiC MPS二极管的重复浪涌电流试验
2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2018-05-01 DOI: 10.1109/ISPSD.2018.8393679
S. Palanisamy, J. Kowalsky, J. Lutz, T. Basler, R. Rupp, Jasmin Moazzami-Fallah
{"title":"Repetitive surge current test of SiC MPS diode with load in bipolar regime","authors":"S. Palanisamy, J. Kowalsky, J. Lutz, T. Basler, R. Rupp, Jasmin Moazzami-Fallah","doi":"10.1109/ISPSD.2018.8393679","DOIUrl":"https://doi.org/10.1109/ISPSD.2018.8393679","url":null,"abstract":"The reliability of power diodes under surge current is an important factor that has to be taken into account for power electronic applications. In this work, latest generation SiC MPS (Merged Pin Schottky) diodes (650V, 1200V, 1700V) with different current classes from Infineon are exposed to repetitive high surge current stress. Furthermore, the temperature was estimated using different methods including direct measurement, Sentaurus TCAD simulation, Cauer network and an analytical model using temperature dependent mobility. It was found that the diodes could withstand a high number of high-current pulses. However, before reaching final destruction, different ageing phenomenon were observed at the unipolar and bipolar regime of the MPS diode. A detailed investigation on the aging mechanisms including failure analysis was performed.","PeriodicalId":166809,"journal":{"name":"2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121166390","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
High accuracy large-signal SPICE model for silicon carbide MOSFET 用于碳化硅MOSFET的高精度大信号SPICE模型
2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2018-05-01 DOI: 10.1109/ISPSD.2018.8393688
F. Hsu, C. Yen, C. Hung, Chwan-Ying Lee, L. Lee, K. Chu, Yafang Li
{"title":"High accuracy large-signal SPICE model for silicon carbide MOSFET","authors":"F. Hsu, C. Yen, C. Hung, Chwan-Ying Lee, L. Lee, K. Chu, Yafang Li","doi":"10.1109/ISPSD.2018.8393688","DOIUrl":"https://doi.org/10.1109/ISPSD.2018.8393688","url":null,"abstract":"This paper provides a method to match characteristics of SiC MOSFET by a simple SPICE model. Besides, this method not only reaches highly approximate results in an accuracy of characteristics compared to commercial SiC SPICE model but also reduces lots of quantities of parameters from modified BSIM model. This method expresses the 1st quadrant ID-VDS and ID-VGS curve well by some additional modified equations. Also, the model development of the 3rd quadrant characteristics, which combines a diode with a JFET model, obtains a good fitting result. Finally, compared to conventional models, the R-square value and normalized RMSD value are significantly improved.","PeriodicalId":166809,"journal":{"name":"2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123213662","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
High voltage capacitive voltage conversion 高压容性电压转换
2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2018-05-01 DOI: 10.1109/ISPSD.2018.8393715
Randall L. Sandusky, A. Hölke
{"title":"High voltage capacitive voltage conversion","authors":"Randall L. Sandusky, A. Hölke","doi":"10.1109/ISPSD.2018.8393715","DOIUrl":"https://doi.org/10.1109/ISPSD.2018.8393715","url":null,"abstract":"A novel high-voltage, ultra-high efficiency monolithic DC-DC Converter is presented. The disclosed architecture was integrated in the X-Fab XT018 SOI process using lateral Super Junction NMOS devices for up to 400V operation. Buck or boost voltage conversion is realized using high-voltage switched-capacitor and gate-driver techniques enabling efficiencies of > 98% peak efficiency, > 97% from 5% to 100% load. The topology is suitable for many applications including charging systems for cell-phones, tablets or other handheld devices, USB power conversion, AC-DC Adapters, DC-DC Point-of-Load (POL) and IoT applications. Block diagrams, simulated and measured results are presented showing the key features of this architecture, areas of interest and the performance summary.","PeriodicalId":166809,"journal":{"name":"2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"256 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123245406","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Characterization of GaN-HEMT in cascode topology and comparison with state of the art-power devices 级联码拓扑GaN-HEMT的特性及与现有功率器件的比较
2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2018-05-01 DOI: 10.1109/ISPSD.2018.8393636
S. Buetow, R. Herzer
{"title":"Characterization of GaN-HEMT in cascode topology and comparison with state of the art-power devices","authors":"S. Buetow, R. Herzer","doi":"10.1109/ISPSD.2018.8393636","DOIUrl":"https://doi.org/10.1109/ISPSD.2018.8393636","url":null,"abstract":"The paper presents a fully static and dynamic characterization and also reliability investigations of a 650V, 28mΩ GaN-HEMT in Cascode-topology. To show the overall performance of GaN-HEMT the output current per chip area (A per mm2) versus switching frequency of a three phase inverter is presented for the 650V GaN-HEMT in comparison to 650V Si-IGBT3 (IFX) and Si-CooLMOS C7 (IFX, with fast Si-FWD and SiC-FWD).","PeriodicalId":166809,"journal":{"name":"2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124008556","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Accelerated thermal fatigue test of metallized ceramic substrates for SiC power modules by repeated four-point bending SiC功率模块金属化陶瓷基板重复四点弯曲加速热疲劳试验
2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2018-05-01 DOI: 10.1109/ISPSD.2018.8393653
H. Miyazaki, Hideki Hyuga, K. Hirao, Hiroshi Sato, H. Yamaguchi, Shoji Iwakiri, H. Hirotsuru
{"title":"Accelerated thermal fatigue test of metallized ceramic substrates for SiC power modules by repeated four-point bending","authors":"H. Miyazaki, Hideki Hyuga, K. Hirao, Hiroshi Sato, H. Yamaguchi, Shoji Iwakiri, H. Hirotsuru","doi":"10.1109/ISPSD.2018.8393653","DOIUrl":"https://doi.org/10.1109/ISPSD.2018.8393653","url":null,"abstract":"Maximum tensile stress in the ceramics during thermal cycle test (from −40 to 250°C) of active metal brazing (AMB) substrate was estimated by the finite element method (FEM) analysis, because such a tensile stress is the driving force of Cu plate delamination from the ceramic plate. In order to accelerate thermal fatigue of the AMB substrate, tensile stress 1.5–2.1 times larger than the maximum thermal stress at −40°C was applied to ceramic plate by four-point bending the AMB substrate at 250°C repeatedly at a frequency of 1 Hz. The time to failure by repeated bending of the SÌ3N4-AMB substrate was less than 1/40 of the time to delamination of the Cu plate by the thermal cycling.","PeriodicalId":166809,"journal":{"name":"2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117117868","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Application-driven device/circuit co-simulation framework for power MOSFET design and technology development 应用驱动的器件/电路联合仿真框架，用于功率MOSFET设计和技术开发
2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2018-05-01 DOI: 10.1109/ISPSD.2018.8393659
T. Sarkar, A. Challa, Kirk Huang, P. Venkatraman, D. Probst
{"title":"Application-driven device/circuit co-simulation framework for power MOSFET design and technology development","authors":"T. Sarkar, A. Challa, Kirk Huang, P. Venkatraman, D. Probst","doi":"10.1109/ISPSD.2018.8393659","DOIUrl":"https://doi.org/10.1109/ISPSD.2018.8393659","url":null,"abstract":"Physics-based device-circuit co-simulation turns out to be an extremely valuable tool to guide and optimize process technology development and device design for high-performance power MOSFETs. It is particularly well-suited to the need of emerging trend of integration of discrete power devices and analog ICs in the same package. In this article, we outline the key features and benefits of such an integrated design framework.","PeriodicalId":166809,"journal":{"name":"2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114240279","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Novel current re-distribution structure for improved and easy-to-manufacturing 24V LDMOS 新型电流再分配结构，用于改进和易于制造的24V LDMOS
2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2018-05-01 DOI: 10.1109/ISPSD.2018.8393661
Cheng-Hua Lin, Yan-Liang Ji, C. Jan, C. W. Hu, K. Chang, H. Kao
{"title":"Novel current re-distribution structure for improved and easy-to-manufacturing 24V LDMOS","authors":"Cheng-Hua Lin, Yan-Liang Ji, C. Jan, C. W. Hu, K. Chang, H. Kao","doi":"10.1109/ISPSD.2018.8393661","DOIUrl":"https://doi.org/10.1109/ISPSD.2018.8393661","url":null,"abstract":"This paper presents a novel structure combined POLY-CAP and P+ Cut Edge which are implemented in s.LDMOS (switching LDMOS) to avoid trapping at active region. s.LDMOS is widely used in SMPS (Switch Mode Power Supply) which requires reliable lifetime and stable turn-on performance. P+ Cut Edge could perfectly solve hump effect while turn-on; with Drain side POLY-CAP, lifetime could be drastically improved under NCS (Non-Conductive Stress) to sustain DC 10 years with comparable BV (Breakdown Voltage) and HCI (Hot Carrier Injection) lifetime.","PeriodicalId":166809,"journal":{"name":"2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123893539","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
首页 上一页 下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：481959085
Book学术官方微信