Reliability investigation with accelerated body diode current stress for 3.3 kV 4H-SiC MOSFETs with various buffer epilayer thickness

Y. Ebiike, Takeshi Murakami, E. Suekawa, Shigehisa Yamamoto, H. Sumitani, M. Imaizumi, M. Tarutani
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引用次数: 9

Abstract

3.3 kV 4H-SiC MOSFETs with various buffer layer thickness has been fabricated in order to investigate the bipolar degradation associated with the expansion of stacking faults (SFs). The body diode stress tests under DC current of 240 A/cm2 were performed at 200 °C. Shifts in specific on-resistance (Ron, sp) and forward voltage (Vf) of body diode were markedly reduced for the MOSFETs with thick buffer layer of 30 μm. This result indicates that the body diode reliability may be improved by suitably designed buffer layer. The photoluminescence (PL) image of these SiC epilayer after the stress tests revealed the SF expansion due to the bipolar current stress was suppressed by the thick buffer layer.
3.3 kV不同缓冲层厚度4H-SiC mosfet的加速体二极管电流应力可靠性研究
为了研究与层错扩展相关的双极退化,制备了具有不同缓冲层厚度的3.3 kV 4H-SiC mosfet。体二极管在直流电流240 A/cm2下,在200℃下进行应力测试。当缓冲层厚度为30 μm时,主体二极管的比导通电阻(Ron, sp)和正向电压(Vf)的位移明显减小。结果表明,适当设计缓冲层可以提高本体二极管的可靠性。应力测试后的光致发光(PL)图像显示,由于双极电流应力引起的SF膨胀被厚缓冲层抑制。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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