2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD)最新文献_第2页

Novel AlGaN/GaN SBDs with nanoscale multi-channel for gradient 2DEG modulation 具有纳米级多通道梯度2DEG调制的新型AlGaN/GaN sbd

2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2018-05-13 DOI: 10.1109/ISPSD.2018.8393638

A. Zhang, Qi Zhou, Chao Yang, Yuanyuan Shi, Changxu Dong, Tong Liu, Yijun Shi, Wanjun Chen, Zhaoji Li, Bo Zhang

{"title":"Novel AlGaN/GaN SBDs with nanoscale multi-channel for gradient 2DEG modulation","authors":"A. Zhang, Qi Zhou, Chao Yang, Yuanyuan Shi, Changxu Dong, Tong Liu, Yijun Shi, Wanjun Chen, Zhaoji Li, Bo Zhang","doi":"10.1109/ISPSD.2018.8393638","DOIUrl":"https://doi.org/10.1109/ISPSD.2018.8393638","url":null,"abstract":"Novel lateral AlGaN/GaN Schottky barrier diodes (SBDs) featuring nanoscale multi-channel for gradient two-dimensional electron gas (2DEG) modulation have been proposed and successfully demonstrated on silicon substrates. The 5 °C low temperature plasma etching with improved resolution is developed to form the nanoscale trenches. Due to the aspect ratio dependent etching, the trenches with different widths and depths can be fabricated in one step etching process. Owing to the small discontinuous etching area of the nanoscale trenches, the lattice strain presented in the original AlGaN/GaN heterostructure is marginally modified. Hence the piezoelectric polarization induced 2DEG can be well maintained and gradually modulated beneath the Schottky contact, which is beneficial for a low turn-on ( VT) and high breakdown voltage (BV). The fabricated SBDs exhibit uniform VT of 0.61±0.02 V and maximum BV of 1317 V. The proposed nanoscale multi-channel structure can also be applied in the gate structure design for normally-off GaN high electron mobility transistors (HEMTs) as well as edge termination for electric-field distribution optimization of power devices.","PeriodicalId":166809,"journal":{"name":"2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126089396","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Influence of the off-state gate-source voltage on the transient drain current response of SiC MOSFETs 失态栅源电压对SiC mosfet瞬态漏极电流响应的影响

2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2018-05-13 DOI: 10.1109/ISPSD.2018.8393599

Christian Unger, M. Pfost

引用次数: 11

Avalanche ruggedness and reverse-bias reliability of SiC MOSFET with integrated junction barrier controlled Schottky rectifier 集成结势垒控制肖特基整流器SiC MOSFET的雪崩耐用性和反偏置可靠性

2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2018-05-13 DOI: 10.1109/ISPSD.2018.8393601

C. Yen, F. Hsu, C. Hung, Chwan-Ying Lee, L. Lee, Yafang Li, K. Chu

{"title":"Avalanche ruggedness and reverse-bias reliability of SiC MOSFET with integrated junction barrier controlled Schottky rectifier","authors":"C. Yen, F. Hsu, C. Hung, Chwan-Ying Lee, L. Lee, Yafang Li, K. Chu","doi":"10.1109/ISPSD.2018.8393601","DOIUrl":"https://doi.org/10.1109/ISPSD.2018.8393601","url":null,"abstract":"A process and a scalable structure were used to implement the SiC MOSFET with integrated junction barrier controlled Schottky diode (JMOS) without area penalty. The JMOS could provide similar on-resistance and drain-source breakdown voltage with the same chip size as the standard double-implanted MOSFET (DMOS). The ideal factor and Schottky barrier height of integrated Schottky diode were 1.13 and 1.22eV for 650V JMOS and 1.11 and 1.27eV for 1200V JMOS. The diode forward voltage drop of JMOS were lower than DMOS when the diode forward current were smaller than 44A for 650V JMOS and 58A for 1200V JMOS. The reverse recovery charge of 650V and 1200V JMOS at 150°C were 22% and 53% lower than corresponding DMOS. The peak reverse recovery current of 650V and 1200V JMOS were 26% and 40% lower than corresponding DMOS. The output capacitance of JMOS were also lower than DMOS. The avalanche energy (Eas) of 650V and 1200V JMOS were 1682mJ and 1270mJ, smaller than the corresponding DMOS, but a 17.2 J/cm2 Eas is still superior to silicon counterparts. The results of diode forward current stress, diode surge current test and 1000 hours high temperature reverse bias test demonstrated that JMOS is reliable.","PeriodicalId":166809,"journal":{"name":"2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130408632","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 15

IGBT with superior long-term switching behavior by asymmetric trench oxide 非对称沟槽氧化物具有优异的长期开关性能的IGBT

2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2018-05-13 DOI: 10.1109/ISPSD.2018.8393593

C. Sandow, P. Brandt, H. Felsl, F. Niedernostheide, F. Pfirsch, H. Schulze, A. Stegner, F. Umbach, F. Santos, W. Wagner

引用次数: 8

6.5 kV field shielded anode (FSA) diode concept with 150C maximum operational temperature capability 6.5 kV场屏蔽阳极(FSA)二极管概念，最大工作温度150℃

2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2018-05-13 DOI: 10.1109/ISPSD.2018.8393594

B. Boksteen, C. Papadopoulos, D. Prindle, A. Kopta, C. Corvasce

引用次数: 2

645 V quasi-vertical GaN power transistors on silicon substrates 硅衬底上645 V准垂直GaN功率晶体管

2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2018-05-13 DOI: 10.1109/ISPSD.2018.8393647

Chao Liu, R. Khadar, E. Matioli

引用次数: 4

Duty-cycle-accelerated hot-carrier degradation and lifetime evaluation for 700V lateral DMOS 700V横向DMOS的占空比加速热载流子退化和寿命评估

2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2018-05-13 DOI: 10.1109/ISPSD.2018.8393667

Siyang Liu, Zhichao Li, Wangran Wu, Weifeng Sun, Shulang Ma, Yuwei Liu, Wei Su, Xiaohong Liu

引用次数: 2

Monolithic integration of GaN-based NMOS digital logic gate circuits with E-mode power GaN MOSHEMTs 基于GaN的NMOS数字逻辑门电路与e型功率GaN moshemt的单片集成

2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2018-05-13 DOI: 10.1109/ISPSD.2018.8393646

Minghua Zhu, E. Matioli

引用次数: 23

Comprehensive investigation on mechanical strain induced performance boosts in LDMOS 机械应变致LDMOS性能提升的综合研究

2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2018-05-13 DOI: 10.1109/ISPSD.2018.8393602

Wangran Wu, Siyang Liu, Jing Zhu, Weifeng Sun

引用次数: 6

Robustness improvement of short-circuit capability by SiC trench-etched double-diffused MOS (TED MOS) SiC蚀刻双扩散MOS (TED MOS)提高短路性能的鲁棒性

2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2018-05-13 DOI: 10.1109/ISPSD.2018.8393697

N. Tega, K. Tani, D. Hisamoto, A. Shima

引用次数: 2