{"title":"基于GaN的NMOS数字逻辑门电路与e型功率GaN moshemt的单片集成","authors":"Minghua Zhu, E. Matioli","doi":"10.1109/ISPSD.2018.8393646","DOIUrl":null,"url":null,"abstract":"In this work, we demonstrate high-performance NMOS GaN-based logic gates including NOT, NAND, and NOR by integration of E/D-mode GaN MOSHEMTs on silicon substrates. The load-to-driver resistance ratio was optimized in these logic gates by using a multi-finger gate design of E-mode GaN MOSHEMT to increase the logic swing voltage and noise margins, and reduce the transition periods. State-of-the-art NMOS inverter was achieved with logic swing voltage of 4.93 V at a supply voltage of 5 V, low-input noise margin of 2.13 V and high-input noise margin of 2.2 V at room temperature. Excellent high temperature performance, at 300°C, was observed with a logic swing of 4.85 V, low-input noise margin of 1.85 V and high-output noise margin of 2.2V. In addition, GaN-based NAND and NOR NMOS logic gates are reported for the first time with very good performance. Finally, the logic gates were monolithically integrated with high-voltage E-mode power transistors, which reveals a significant step forward towards monolithic integration of GaN power transistors with gate drivers.","PeriodicalId":166809,"journal":{"name":"2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"72 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"23","resultStr":"{\"title\":\"Monolithic integration of GaN-based NMOS digital logic gate circuits with E-mode power GaN MOSHEMTs\",\"authors\":\"Minghua Zhu, E. Matioli\",\"doi\":\"10.1109/ISPSD.2018.8393646\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this work, we demonstrate high-performance NMOS GaN-based logic gates including NOT, NAND, and NOR by integration of E/D-mode GaN MOSHEMTs on silicon substrates. The load-to-driver resistance ratio was optimized in these logic gates by using a multi-finger gate design of E-mode GaN MOSHEMT to increase the logic swing voltage and noise margins, and reduce the transition periods. State-of-the-art NMOS inverter was achieved with logic swing voltage of 4.93 V at a supply voltage of 5 V, low-input noise margin of 2.13 V and high-input noise margin of 2.2 V at room temperature. Excellent high temperature performance, at 300°C, was observed with a logic swing of 4.85 V, low-input noise margin of 1.85 V and high-output noise margin of 2.2V. In addition, GaN-based NAND and NOR NMOS logic gates are reported for the first time with very good performance. Finally, the logic gates were monolithically integrated with high-voltage E-mode power transistors, which reveals a significant step forward towards monolithic integration of GaN power transistors with gate drivers.\",\"PeriodicalId\":166809,\"journal\":{\"name\":\"2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD)\",\"volume\":\"72 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2018-05-13\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"23\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISPSD.2018.8393646\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISPSD.2018.8393646","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Monolithic integration of GaN-based NMOS digital logic gate circuits with E-mode power GaN MOSHEMTs
In this work, we demonstrate high-performance NMOS GaN-based logic gates including NOT, NAND, and NOR by integration of E/D-mode GaN MOSHEMTs on silicon substrates. The load-to-driver resistance ratio was optimized in these logic gates by using a multi-finger gate design of E-mode GaN MOSHEMT to increase the logic swing voltage and noise margins, and reduce the transition periods. State-of-the-art NMOS inverter was achieved with logic swing voltage of 4.93 V at a supply voltage of 5 V, low-input noise margin of 2.13 V and high-input noise margin of 2.2 V at room temperature. Excellent high temperature performance, at 300°C, was observed with a logic swing of 4.85 V, low-input noise margin of 1.85 V and high-output noise margin of 2.2V. In addition, GaN-based NAND and NOR NMOS logic gates are reported for the first time with very good performance. Finally, the logic gates were monolithically integrated with high-voltage E-mode power transistors, which reveals a significant step forward towards monolithic integration of GaN power transistors with gate drivers.