用于高压SoC应用的漏极扩展FinFET器件的性能和可靠性见解

2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2018-05-13 DOI:10.1109/ISPSD.2018.8393605

B. Kumar, Milova Paul, M. Shrivastava, H. Gossner

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引用次数: 6

摘要

本文讨论了漏极扩展FinFET器件的设计以及与性能和可靠性相关的挑战。详细阐述了Fin高电压设计的性能与可靠性权衡的物理见解，并与平面设计进行了比较(demo)。讨论了翅片宽度离散化对ESD可靠性、安全操作区域和HCI可靠性的影响。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Performance and reliability insights of drain extended FinFET devices for high voltage SoC applications

In this paper1, Drain extended FinFET device design and the challenges associated with the performance and reliability are discussed. Physical insights into the performance vs. reliability trade-off for the Fin enabled high voltage designs is elaborated and compared with their planar counterpart (DeMOS). Effect of Fin width discretization over ESD reliability, Safe Operating Area and HCI reliability are discussed.

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2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD)

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