1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC最新文献

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One-transistor-cell multiple-valued CAM for a collision detection VLSI processor 碰撞检测VLSI处理器的单晶体管单元多值CAM
T. Hanyu, N. Kanagawa, M. Kameyama
{"title":"One-transistor-cell multiple-valued CAM for a collision detection VLSI processor","authors":"T. Hanyu, N. Kanagawa, M. Kameyama","doi":"10.1109/ISSCC.1996.488616","DOIUrl":"https://doi.org/10.1109/ISSCC.1996.488616","url":null,"abstract":"Parallel search and parallel comparison are major advantages of content-addressable memories (CAMs) over random-access memories. However, a CAM is more complex and has lower storage density than a conventional address-based memory because of the overhead involved in the storage, comparison, manipulation, and output-selection logic. A CAM based on multiple-valued logic is proposed for high-speed word-parallel magnitude comparison. A typical application of the multiple-valued CAM is a collision detection VLSI processor for intelligent vehicles.","PeriodicalId":162539,"journal":{"name":"1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC","volume":"174 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121137534","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
RF analog and digital circuits in SiGe technology SiGe技术中的射频模拟和数字电路
John R. Long, Miles A. Copeland, Stephen J. Kovacic, Duljit S. Malhi, David L. Harame
{"title":"RF analog and digital circuits in SiGe technology","authors":"John R. Long, Miles A. Copeland, Stephen J. Kovacic, Duljit S. Malhi, David L. Harame","doi":"10.1109/ISSCC.1996.488523","DOIUrl":"https://doi.org/10.1109/ISSCC.1996.488523","url":null,"abstract":"The performance of a commercially viable SiGe-HBT technology is demonstrated in analog and digital communications applications. The measurements show that circuits fabricated in this technology are capable of fulfilling application requirements for RF analog in the 1-5 GHz range and for high-speed digital circuits at or above the 10 Gb/s range, with potentially lower power, lower cost and higher reliability compared to other high-speed/RF technology options.","PeriodicalId":162539,"journal":{"name":"1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125126344","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 54
A 1 MB, 100 MHz integrated L2 cache memory with 128b interface and ECC protection 1mb, 100mhz集成L2缓存存储器,128b接口和ECC保护
G. Giacalone, R. Busch, F. Creed, A. Davidovich, S. Divakaruni, C. Drake, C. Ematrudo, J. Fifield, M. Hodges, W. Howell, P. Jenkins, M. Kozyrczak, C. Miller, T. Obremski, C. Reed, G. Rohrbaugh, M. Vincent, T. von Reyn, J. Zimmerman
{"title":"A 1 MB, 100 MHz integrated L2 cache memory with 128b interface and ECC protection","authors":"G. Giacalone, R. Busch, F. Creed, A. Davidovich, S. Divakaruni, C. Drake, C. Ematrudo, J. Fifield, M. Hodges, W. Howell, P. Jenkins, M. Kozyrczak, C. Miller, T. Obremski, C. Reed, G. Rohrbaugh, M. Vincent, T. von Reyn, J. Zimmerman","doi":"10.1109/ISSCC.1996.488721","DOIUrl":"https://doi.org/10.1109/ISSCC.1996.488721","url":null,"abstract":"Several cache-DRAMs have been reported, but all require multiple chips to implement an L2 cache system. The advent of 20 ns, 16 Mb DRAM technology has made a high-speed single-chip 1MB cache possible, replacing multiple SRAM and logic modules, saving board space and reducing power. Multichip-module (MCM) packaging further optimizes the electrical characteristics of the processor-cache connection. An in-line level-2 1 MB cache chip that has DRAM density contains high-speed SRAM and MCM technology.","PeriodicalId":162539,"journal":{"name":"1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121928892","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
15 /spl mu/m solder bonding of GaAs/AlGaAs MQW devices to MOSIS 0.8 /spl mu/m CMOS for 1 Gb/s two-beam smart-pixel receiver/transmitter 15 /spl mu/m的GaAs/AlGaAs MQW器件焊接到MOSIS 0.8 /spl mu/m CMOS,用于1gb /s双波束智能像素接收/发送
T. K. Woodward, A. Krishnamoorthy, K. Goossen, J. A. Walker, A. Lentine, R. A. Novotny, L. D’asaro, L. Chirovsky, S. Hui, B. Tseng, D. Kossives, D. Dahringer, R. Leibenguth, J. Cunningham, W. Jan, D. Miller
{"title":"15 /spl mu/m solder bonding of GaAs/AlGaAs MQW devices to MOSIS 0.8 /spl mu/m CMOS for 1 Gb/s two-beam smart-pixel receiver/transmitter","authors":"T. K. Woodward, A. Krishnamoorthy, K. Goossen, J. A. Walker, A. Lentine, R. A. Novotny, L. D’asaro, L. Chirovsky, S. Hui, B. Tseng, D. Kossives, D. Dahringer, R. Leibenguth, J. Cunningham, W. Jan, D. Miller","doi":"10.1109/ISSCC.1996.488737","DOIUrl":"https://doi.org/10.1109/ISSCC.1996.488737","url":null,"abstract":"A two-beam optical repeater circuit operates to 1 Gb/s, consumes 10 mW, occupies about 1100 /spl mu/m/sup 2/, and is realized with a technology capable of providing thousands of optical inputs and outputs to foundry-grade VLSI silicon CMOS circuitry. The technology provides this capability by attaching GaAs/AlGaAs multiple-quantum-well (MQW) modulators and detectors to VLSI CMOS with flip-chip solder bonding. The main unique features are summarized.","PeriodicalId":162539,"journal":{"name":"1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122209087","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Circuit techniques for 10 and 20 Gb/s clock recovery using a fully balanced narrowband regenerative frequency divider with 0.3 /spl mu/m HEMTs [SDH/SONET] 采用0.3 /spl mu/m HEMTs的全平衡窄带再生分频器实现10gb /s和20gb /s时钟恢复的电路技术
Zhi-Gong Wang, M. Berroth, A. Thiede, M. Rieger-Motzer, P. Hofmann, A. Hulsmann, K. Kohler, B. Raynor, J. Schneider, D. Briggmann
{"title":"Circuit techniques for 10 and 20 Gb/s clock recovery using a fully balanced narrowband regenerative frequency divider with 0.3 /spl mu/m HEMTs [SDH/SONET]","authors":"Zhi-Gong Wang, M. Berroth, A. Thiede, M. Rieger-Motzer, P. Hofmann, A. Hulsmann, K. Kohler, B. Raynor, J. Schneider, D. Briggmann","doi":"10.1109/ISSCC.1996.488572","DOIUrl":"https://doi.org/10.1109/ISSCC.1996.488572","url":null,"abstract":"The circuit consists of four subcircuits: the preprocessor, the narrowband regenerative frequency divider (NRFD), the phase-shifting amplifier, and the limiting amplifier. The CR circuit is fully-balanced and can be operated in two modes. At 10 Gb/s input data, the tank circuit of the preprocessor resonates at the second harmonic of the clock frequency. This mode can be used for 10 Gb/s direct data decision. At 20 Gb/s the tank circuit resonates at the fundamental frequency of the clock signal. This mode is optimal for a 20 Gb/s parallel data decision.","PeriodicalId":162539,"journal":{"name":"1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129078089","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A 768 k embedded DRAM for 1.244 Gb/s ATM switch in a 0.8 /spl mu/m logic process 在0.8 /spl mu/m的逻辑过程中,用于1.244 Gb/s ATM交换机的768 k嵌入式DRAM
P. Gillingham, B. Hold, I. Mes, C. O'Connell, P. Schofield, K. Skjaveland, R. Torrance, T. Wojcicki, H. Chow
{"title":"A 768 k embedded DRAM for 1.244 Gb/s ATM switch in a 0.8 /spl mu/m logic process","authors":"P. Gillingham, B. Hold, I. Mes, C. O'Connell, P. Schofield, K. Skjaveland, R. Torrance, T. Wojcicki, H. Chow","doi":"10.1109/ISSCC.1996.488615","DOIUrl":"https://doi.org/10.1109/ISSCC.1996.488615","url":null,"abstract":"This 256 k DRAM macrocell in a 0.8 /spl mu/m single-poly, double-metal, p-substrate, n-well logic process offers 3 times the density of an embedded SRAM without special processing steps. Robust data retention and soft-error performance are achieved by use of a p-channel 1T cell featuring a flexible high-bandwidth interface to support a variety of applications. Three macrocells are used for a 768 k queue memory in a 1.244 Gb/s ATM switch ASIC.","PeriodicalId":162539,"journal":{"name":"1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123666206","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Si/SiGe HBT technology for low-cost monolithic microwave integrated circuits 低成本单片微波集成电路的Si/SiGe HBT技术
L. Larson, M. Case, S. Rosenbaum, D. Rensch, P. Macdonald, M. Matloubian, M. Chen, D. Harame, J. Malinowski, B. Meyerson, M. Gilbert, S. Maas
{"title":"Si/SiGe HBT technology for low-cost monolithic microwave integrated circuits","authors":"L. Larson, M. Case, S. Rosenbaum, D. Rensch, P. Macdonald, M. Matloubian, M. Chen, D. Harame, J. Malinowski, B. Meyerson, M. Gilbert, S. Maas","doi":"10.1109/ISSCC.1996.488522","DOIUrl":"https://doi.org/10.1109/ISSCC.1996.488522","url":null,"abstract":"This silicon-based microwave integrated-circuit technology is suitable for implementation of high-performance low-cost active circuits from 5-25 GHz. This technology promises to dramatically reduce the cost of microwave integrated circuit technology by utilizing manufacturable, high-yield, silicon IC processing, and at the same time enable more highly integrated implementations of microwave transceiver components. A variety of microwave integrated circuits implemented in this technology include mixers, frequency dividers, amplifiers and VCOs, demonstrating feasibility of silicon integrated circuit technology for implementation of low-cost integrated circuits in the upper microwave spectrum.","PeriodicalId":162539,"journal":{"name":"1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126577736","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 44
TCAD for analog circuit applications: virtual devices and instruments TCAD用于模拟电路应用:虚拟设备和仪器
R. Dutton, B. Troyanovsky, Zhiping Yu, E. Kan, K. Wang, Tao Chen, T. Amborg
{"title":"TCAD for analog circuit applications: virtual devices and instruments","authors":"R. Dutton, B. Troyanovsky, Zhiping Yu, E. Kan, K. Wang, Tao Chen, T. Amborg","doi":"10.1109/ISSCC.1996.488521","DOIUrl":"https://doi.org/10.1109/ISSCC.1996.488521","url":null,"abstract":"Capabilities for analog modeling of advanced transistors are demonstrated based on tools and techniques developed specifically to support technology development. In addition, providing support for more accurate analog modeling, there is the opportunity to predict technology dependencies and therefore to selectively target technology optimization for analog performance. The term \"technology files\" is well-known among circuit designers and specifically means the relevant circuit modeling information that contains technology dependencies. Technology computer-aided design (TCAD) provides powerful analog capabilities to directly predict not only the technology files but also a wide range of other critical behavior information about devices and circuits that depend directly on technology.","PeriodicalId":162539,"journal":{"name":"1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130862334","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A 0.9 V 1.2 mA 200 MHz BiCMOS single-chip narrow-band FM receiver 一个0.9 V 1.2 mA 200 MHz BiCMOS单片窄带调频接收机
M. Pardoen, J. Gerrits, V. von Kaenel
{"title":"A 0.9 V 1.2 mA 200 MHz BiCMOS single-chip narrow-band FM receiver","authors":"M. Pardoen, J. Gerrits, V. von Kaenel","doi":"10.1109/ISSCC.1996.488712","DOIUrl":"https://doi.org/10.1109/ISSCC.1996.488712","url":null,"abstract":"Low-power single-cell battery-operated fully-featured radio receivers, with a minimum of external components are hard to find. Classical low-voltage heterodyne receivers consisting of bipolar transistor arrays require 50 to 60 external components to realize off-chip selectivity, filtering, demodulation, audio processing, etc. Zero or low intermediate frequency (IF) bipolar integrated circuit (IC) receivers with some on-chip base-band processing circuits require 25 to 40 components, but do not work at 0.9 V or drain more than 10 mA. This BiCMOS receiver IC is a full-featured single-conversion low IF narrow-band FM receiver that needs only 4 to 7 external components. This is made possible by a fully-integrated delay-line FM demodulator using parallelism that enables both automatic-frequency control (AFC) and muting to be realized at IF. Full functionality down to 0.9 V is obtained by ac coupling at radio frequencies (RF) and bulk forward biasing in the CMOS analog and digital building blocks. The receiver uses a BiCMOS process featuring vertical 3.6 /spl mu/m npn and pnp BJTs and 1.2 /spl mu/m 0.86 V V/sub Tmax/ MOS transistors. The chip area is 22 mm/sup 2/.","PeriodicalId":162539,"journal":{"name":"1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC","volume":"87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132705661","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A low-power CMOS chipset for spread spectrum communications 用于扩频通信的低功耗CMOS芯片组
S. Sheng, L. Lynn, J. Peroulas, Kevin Stone, I.D. O'Donnell, R. Brodersen
{"title":"A low-power CMOS chipset for spread spectrum communications","authors":"S. Sheng, L. Lynn, J. Peroulas, Kevin Stone, I.D. O'Donnell, R. Brodersen","doi":"10.1109/ISSCC.1996.488711","DOIUrl":"https://doi.org/10.1109/ISSCC.1996.488711","url":null,"abstract":"In future personal communication services, high-bandwidth multimedia data will be delivered over wireless pico-cellular networks to high densities of users. The system described here is designed to simultaneously supply 1 Mb/s to up to 50 users in a single cell, requiring a system bandwidth in excess of 50 Mb/s. The use of spread-spectrum techniques, in particular direct sequence code-division multiple access (CDMA), provides a multiple-access strategy to maintain parallel, separate streams of real-time data to all users, and to reduce sensitivity to multipath, narrow band fades, and interference present in the radio environment. Three chips in standard digital 0.8 /spl mu/m CMOS technology implement the critical parts of a spread spectrum transceiver: the digital modulator; the analog receiver front-end and ADC; and the digital receiver baseband processor. The transmit system transmitter is based loosely on the US IS-95 digital cellular CDMA standard, but at more than an order of magnitude higher date rate.","PeriodicalId":162539,"journal":{"name":"1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123906394","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 89
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