Circuit techniques for 10 and 20 Gb/s clock recovery using a fully balanced narrowband regenerative frequency divider with 0.3 /spl mu/m HEMTs [SDH/SONET]

Abstract

The circuit consists of four subcircuits: the preprocessor, the narrowband regenerative frequency divider (NRFD), the phase-shifting amplifier, and the limiting amplifier. The CR circuit is fully-balanced and can be operated in two modes. At 10 Gb/s input data, the tank circuit of the preprocessor resonates at the second harmonic of the clock frequency. This mode can be used for 10 Gb/s direct data decision. At 20 Gb/s the tank circuit resonates at the fundamental frequency of the clock signal. This mode is optimal for a 20 Gb/s parallel data decision.