在0.8 /spl mu/m的逻辑过程中，用于1.244 Gb/s ATM交换机的768 k嵌入式DRAM

1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC Pub Date : 1996-02-08 DOI:10.1109/ISSCC.1996.488615

P. Gillingham, B. Hold, I. Mes, C. O'Connell, P. Schofield, K. Skjaveland, R. Torrance, T. Wojcicki, H. Chow

{"title":"在0.8 /spl mu/m的逻辑过程中，用于1.244 Gb/s ATM交换机的768 k嵌入式DRAM","authors":"P. Gillingham, B. Hold, I. Mes, C. O'Connell, P. Schofield, K. Skjaveland, R. Torrance, T. Wojcicki, H. Chow","doi":"10.1109/ISSCC.1996.488615","DOIUrl":null,"url":null,"abstract":"This 256 k DRAM macrocell in a 0.8 /spl mu/m single-poly, double-metal, p-substrate, n-well logic process offers 3 times the density of an embedded SRAM without special processing steps. Robust data retention and soft-error performance are achieved by use of a p-channel 1T cell featuring a flexible high-bandwidth interface to support a variety of applications. Three macrocells are used for a 768 k queue memory in a 1.244 Gb/s ATM switch ASIC.","PeriodicalId":162539,"journal":{"name":"1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC","volume":"7 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1996-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"A 768 k embedded DRAM for 1.244 Gb/s ATM switch in a 0.8 /spl mu/m logic process\",\"authors\":\"P. Gillingham, B. Hold, I. Mes, C. O'Connell, P. Schofield, K. Skjaveland, R. Torrance, T. Wojcicki, H. Chow\",\"doi\":\"10.1109/ISSCC.1996.488615\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This 256 k DRAM macrocell in a 0.8 /spl mu/m single-poly, double-metal, p-substrate, n-well logic process offers 3 times the density of an embedded SRAM without special processing steps. Robust data retention and soft-error performance are achieved by use of a p-channel 1T cell featuring a flexible high-bandwidth interface to support a variety of applications. Three macrocells are used for a 768 k queue memory in a 1.244 Gb/s ATM switch ASIC.\",\"PeriodicalId\":162539,\"journal\":{\"name\":\"1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC\",\"volume\":\"7 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1996-02-08\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISSCC.1996.488615\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.1996.488615","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 3

摘要

这款256 k的DRAM宏单元采用0.8 /spl mu/m的单聚、双金属、p衬底、n阱逻辑工艺，其密度是嵌入式SRAM的3倍，无需特殊处理步骤。通过使用具有灵活的高带宽接口以支持各种应用的p通道1T单元，实现了稳健的数据保留和软错误性能。在1.244 Gb/s的ATM交换机ASIC中，768 k队列内存使用了三个宏单元。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

A 768 k embedded DRAM for 1.244 Gb/s ATM switch in a 0.8 /spl mu/m logic process

This 256 k DRAM macrocell in a 0.8 /spl mu/m single-poly, double-metal, p-substrate, n-well logic process offers 3 times the density of an embedded SRAM without special processing steps. Robust data retention and soft-error performance are achieved by use of a p-channel 1T cell featuring a flexible high-bandwidth interface to support a variety of applications. Three macrocells are used for a 768 k queue memory in a 1.244 Gb/s ATM switch ASIC.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC

自引率

0.00%

发文量