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1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC最新文献

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A 0.25 mW 13 b passive /spl Sigma//spl Delta/ modulator for a 10 MHz IF input 一个0.25 mW 13 b无源/spl Sigma//spl Delta/调制器，用于10 MHz中频输入
1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC Pub Date : 1996-02-08 DOI: 10.1109/ISSCC.1996.488513
Feng Chen, B. Leung
{"title":"A 0.25 mW 13 b passive /spl Sigma//spl Delta/ modulator for a 10 MHz IF input","authors":"Feng Chen, B. Leung","doi":"10.1109/ISSCC.1996.488513","DOIUrl":"https://doi.org/10.1109/ISSCC.1996.488513","url":null,"abstract":"Combining /spl Sigma//spl Delta/ modulator with mixing achieves frequency translation and A/D conversion in a single step, simplifying analog circuitry and saving power. Further power efficiency can be achieved by a /spl Sigma//spl Delta/ modulator with a passive loop filter. Because this involves direct conversion, the signal is always mixed down to dc irrespective of the pole locations of loop filter and therefore the null position of the quantization noise power spectrum density is insensitive to the parasitics. A passive switched-capacitor modulator with a built-in passive mixer digitizes a 10 MHz IF signal. Due to the lack of gain in the passive loop filter, a switch-only gain-boost network provides gain without using active circuitry.","PeriodicalId":162539,"journal":{"name":"1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129152130","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A 2.7 in. 1.3 MPixel driver-integrated poly-Si TFT-LCD for multimedia projectors 2.7英寸。1.3万像素驱动集成多晶硅TFT-LCD多媒体投影仪
1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC Pub Date : 1996-02-08 DOI: 10.1109/ISSCC.1996.488566
H. Asada, K. Hirata, K. Ozawa, K. Nakamura, H. Tanabe, K. Sera, K. Hamada, K. Mochizuki, S. Ohi, S. Saitoh, F. Okumura, S. Kaneko
{"title":"A 2.7 in. 1.3 MPixel driver-integrated poly-Si TFT-LCD for multimedia projectors","authors":"H. Asada, K. Hirata, K. Ozawa, K. Nakamura, H. Tanabe, K. Sera, K. Hamada, K. Mochizuki, S. Ohi, S. Saitoh, F. Okumura, S. Kaneko","doi":"10.1109/ISSCC.1996.488566","DOIUrl":"https://doi.org/10.1109/ISSCC.1996.488566","url":null,"abstract":"The rapid progress of multimedia demands liquid crystal display (LCD) projectors that can display computer data, such as video-graphic arrays (VGA), super-video-graphic arrays (SVGA), extended-graphic arrays (XGA) and super-extended-graphic arrays (SXGA). One of the major challenges for poly-Si TFT drivers in such multi-scan LCDs is displaying as black in the peripheral region around the picture during a blanking period. Using conventional shift register driver circuits, the scanning speed in the up-and-down no-picture region is too high for pixel TFTs to write signals for black. Although decoder driver circuits for multi-scan operation have been introduced into an HDTV poly-Si TFT-LCD, they require many address signals and logic gates. These increase circuit area and thereby decrease the manufacturing yields. Poly-Si TFT drivers use a combination of bi-directional shift registers and decoder circuits to solve the above problems for a 2.7 in, 1.3 Mpixel TFT LCD light valve.","PeriodicalId":162539,"journal":{"name":"1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC","volume":"118 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133929405","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A GaAs RF transceiver IC for 1.9 GHz digital mobile communication systems 一种用于1.9 GHz数字移动通信系统的GaAs射频收发器IC
1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC Pub Date : 1996-02-08 DOI: 10.1109/ISSCC.1996.488708
K. Yamamoto, K. Maemura, Y. Ohta, N. Kasai, M. Noda, H. Yuura, Y. Yoshii, M. Nakayama, T. Takagi, M. Otsubo
{"title":"A GaAs RF transceiver IC for 1.9 GHz digital mobile communication systems","authors":"K. Yamamoto, K. Maemura, Y. Ohta, N. Kasai, M. Noda, H. Yuura, Y. Yoshii, M. Nakayama, T. Takagi, M. Otsubo","doi":"10.1109/ISSCC.1996.488708","DOIUrl":"https://doi.org/10.1109/ISSCC.1996.488708","url":null,"abstract":"A 3.4 V single power supply GaAs single-chip RF transceiver IC for 1.9 GHz digital mobile communication systems such as the Japanese Personal Handy Phone System (PHS) consists of both analog and digital circuits. The analog circuits contain a power amplifier (PA), an SPDT switch (SW), two attenuators (ATTs) for transmitting and receiving modes, and a low-noise amplifier (LNA). The digital circuits contain a negative voltage generator (NVG) for single voltage operation and a logic circuit to control the analog circuits and the NVG.","PeriodicalId":162539,"journal":{"name":"1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115887800","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
A 55 ns 0.35 /spl mu/m 5 V-only 16 M flash memory with deep-power-down 一个55 ns 0.35 /spl mu/m 5 V-only 16 m闪存，深度掉电
1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC Pub Date : 1996-02-08 DOI: 10.1109/ISSCC.1996.488507
B. Venkatesh, M. Chung, S. Govindachar, V. Santurkar, C. Bill, R. Gutala, D. Zhou, J. Yu, M. Van Buskirk, S. Kawamura, K. Kurihara, H. Kawashima, H. Watanabe
{"title":"A 55 ns 0.35 /spl mu/m 5 V-only 16 M flash memory with deep-power-down","authors":"B. Venkatesh, M. Chung, S. Govindachar, V. Santurkar, C. Bill, R. Gutala, D. Zhou, J. Yu, M. Van Buskirk, S. Kawamura, K. Kurihara, H. Kawashima, H. Watanabe","doi":"10.1109/ISSCC.1996.488507","DOIUrl":"https://doi.org/10.1109/ISSCC.1996.488507","url":null,"abstract":"An embedded 5 V only 16 M flash memory has an on-chip state machine that generates embedded program and erase algorithms, eliminating system execution of these operations. The system issues a series of commands decoded by the state machine for on-chip execution. It is a /spl times/8 part with a read/busy pin to indicate to the system if the part is in an embedded mode, and a RESETB pin to terminate any operation being executed by the state machine and reset the part to the read mode. Erase is by applying a negative voltage to the control gate of the array and a positive voltage VS to the sector array source.","PeriodicalId":162539,"journal":{"name":"1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132079644","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
200 MHz superscalar RISC processor circuit design issues 200mhz超标量RISC处理器电路设计问题
1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC Pub Date : 1996-02-08 DOI: 10.1109/ISSCC.1996.488715
N. Vasseghi, P. Koike, L. Yang, D. Freitas, R. Conrad, A. Bomdica, S. Gupta, Moon-Yee Wang, R. Chang, W. Chan, C. Lee, F. Lutz, F. Leu, H. Nguyen, Q. Nasir
{"title":"200 MHz superscalar RISC processor circuit design issues","authors":"N. Vasseghi, P. Koike, L. Yang, D. Freitas, R. Conrad, A. Bomdica, S. Gupta, Moon-Yee Wang, R. Chang, W. Chan, C. Lee, F. Lutz, F. Leu, H. Nguyen, Q. Nasir","doi":"10.1109/ISSCC.1996.488715","DOIUrl":"https://doi.org/10.1109/ISSCC.1996.488715","url":null,"abstract":"This processor is a dynamic issue five-way superscalar RISC microprocessor that implements the 64 bit MIPS-4 instruction set architecture. It is a single chip implementation containing a central processing unit, floating point unit, 32 kB each instruction and data caches, and secondary cache control. It fetches and decodes 4 instructions per cycle and dynamically issues them to 5 fully-pipelined execution units after dependency resolution. Instructions are issued and completed out of order, but graduated in program order. Register renaming resolves dependencies between instructions. The 16.6/spl times/17.9 mm/sup 2/ die contains 6.8 M transistors in 3.3 V, 4-layer metal 0.35 /spl mu/m CMOS. The fourth-layer metal is twice the thickness of third- and second-layer metal and is used for main clock tree and global power distribution.","PeriodicalId":162539,"journal":{"name":"1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132773122","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Advances in neuron-MOS applications 神经元- mos应用进展
1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC Pub Date : 1996-02-08 DOI: 10.1109/ISSCC.1996.488629
T. Shibata, T. Nakai, Ning Mei Yu, Y. Yamashita, M. Konda, T. Ohmi
{"title":"Advances in neuron-MOS applications","authors":"T. Shibata, T. Nakai, Ning Mei Yu, Y. Yamashita, M. Konda, T. Ohmi","doi":"10.1109/ISSCC.1996.488629","DOIUrl":"https://doi.org/10.1109/ISSCC.1996.488629","url":null,"abstract":"This paper shows how computationally-expensive problems like image processing can be handled in real time with little hardware by neuron-MOS (/spl upsi/MOS) circuit technology. In digital signal processing, real-world data (analog, massive in quantities, low-precision and ambiguous) are A/D converted upon acquisition, including inherent noise and distortion, and then are bit-by-bit computed based on rigorous Boolean algebra. In moving-image processing for instance, this requires extraordinary computational powers of DSPs and MPUs, making real-time response of electronic systems unrealistic. Introduction of analog processing would lessen the difficulty, but cost must be traded off for accuracy. Analog/digital merged computation using /spl upsi/MOS circuits features the flexibility of analog processing but preserving the rigorousness of digital. Highly-parallel analog processing is performed for a large volume of analog input data, that is immediately followed by the binary decision of /spl upsi/MOS gates, resulting in the output of digital codes. Real-world data are directly compressed to digital codes without A/D conversion. The power of this scheme is demonstrated in applications to motion vector search in a few hundred nanoseconds and real-time center-of-mass tracing of a moving object and to building real-time event recognition hardware.","PeriodicalId":162539,"journal":{"name":"1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC","volume":"106 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123621192","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 29
Integrated ultraviolet sensor system with on-chip 1 G/spl Omega/ transimpedance amplifier 集成紫外传感器系统，片上1g /spl ω /跨阻放大器
1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC Pub Date : 1996-02-08 DOI: 10.1109/ISSCC.1996.488639
D. Bolliger, P. Malcovati, A. Haberli, H. Baltes, P. Sarro, F. Maloberti
{"title":"Integrated ultraviolet sensor system with on-chip 1 G/spl Omega/ transimpedance amplifier","authors":"D. Bolliger, P. Malcovati, A. Haberli, H. Baltes, P. Sarro, F. Maloberti","doi":"10.1109/ISSCC.1996.488639","DOIUrl":"https://doi.org/10.1109/ISSCC.1996.488639","url":null,"abstract":"The output current delivered by photo-diodes with enhanced ultraviolet (UV) responsivity is in most cases small, thus requiring an interface circuit with high current gain. Generally, this is achieved using discrete components. This integrated system includes a 1G/spl Omega/ transimpedance stage and an IC-compatible UV photo-diode on a single chip. The industrial application motivating this work is flame detection for combustion monitoring.","PeriodicalId":162539,"journal":{"name":"1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125021597","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Analog CMOS photosensitive array for solar illumination monitoring 用于太阳照度监测的模拟CMOS光敏阵列
1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC Pub Date : 1996-02-08 DOI: 10.1109/ISSCC.1996.488529
P. Venier, O. Landolt, P. Debergh, X. Arreguit
{"title":"Analog CMOS photosensitive array for solar illumination monitoring","authors":"P. Venier, O. Landolt, P. Debergh, X. Arreguit","doi":"10.1109/ISSCC.1996.488529","DOIUrl":"https://doi.org/10.1109/ISSCC.1996.488529","url":null,"abstract":"This analog chip, used in conjunction with a dedicated optical front-end, delivers azimuth, elevation and intensity of the sun as three independent continuous signals. This eliminates external processing, and eases implementation of the sensor in a system.","PeriodicalId":162539,"journal":{"name":"1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC","volume":"219 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115587808","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
A 12 mA triple-conversion receiver for GPS 用于GPS的12毫安三转换接收器
1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC Pub Date : 1996-02-08 DOI: 10.1109/ISSCC.1996.488621
F. Piazza, Qiuting Huang
{"title":"A 12 mA triple-conversion receiver for GPS","authors":"F. Piazza, Qiuting Huang","doi":"10.1109/ISSCC.1996.488621","DOIUrl":"https://doi.org/10.1109/ISSCC.1996.488621","url":null,"abstract":"The circuits reported here form a complete GPS receiver for the civilian L1 band. Triple-conversion architecture minimizes the number of components working at the highest frequency and thus power consumption, while the integration of the 2nd IF filter reduces the complexity of the receiver to a level comparable to that of a single superhet. The immediate application of such an integrated receiver is to provide GPS time reference for small, portable (wearable) consumer products. Low power consumption is a primary requirement. The power supply is 2.4 V to 3.5 V from a lithium battery.","PeriodicalId":162539,"journal":{"name":"1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121124081","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A sub-nanosecond 0.5 /spl mu/m 64 b adder design 亚纳秒0.5 /spl mu/m 64b加法器设计
1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC Pub Date : 1996-02-08 DOI: 10.1109/ISSCC.1996.488718
S. Naffziger
{"title":"A sub-nanosecond 0.5 /spl mu/m 64 b adder design","authors":"S. Naffziger","doi":"10.1109/ISSCC.1996.488718","DOIUrl":"https://doi.org/10.1109/ISSCC.1996.488718","url":null,"abstract":"A sub-nanosecond 64 b adder in 0.5 /spl mu/m CMOS forms the basis for the integer and floating point execution units. Integrating dual-rail dynamic CMOS and use of Ling's equations, the adder is composed of 7k FETs in 0.246 mm/sup 2/ and performs a full 64 b add, operands to result in <1 ns (7 fanout of 4 inverter delays) under nominal conditions.","PeriodicalId":162539,"journal":{"name":"1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127008798","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 41
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