200 MHz superscalar RISC processor circuit design issues

Abstract

This processor is a dynamic issue five-way superscalar RISC microprocessor that implements the 64 bit MIPS-4 instruction set architecture. It is a single chip implementation containing a central processing unit, floating point unit, 32 kB each instruction and data caches, and secondary cache control. It fetches and decodes 4 instructions per cycle and dynamically issues them to 5 fully-pipelined execution units after dependency resolution. Instructions are issued and completed out of order, but graduated in program order. Register renaming resolves dependencies between instructions. The 16.6/spl times/17.9 mm/sup 2/ die contains 6.8 M transistors in 3.3 V, 4-layer metal 0.35 /spl mu/m CMOS. The fourth-layer metal is twice the thickness of third- and second-layer metal and is used for main clock tree and global power distribution.