B. Venkatesh, M. Chung, S. Govindachar, V. Santurkar, C. Bill, R. Gutala, D. Zhou, J. Yu, M. Van Buskirk, S. Kawamura, K. Kurihara, H. Kawashima, H. Watanabe
{"title":"一个55 ns 0.35 /spl mu/m 5 V-only 16 m闪存,深度掉电","authors":"B. Venkatesh, M. Chung, S. Govindachar, V. Santurkar, C. Bill, R. Gutala, D. Zhou, J. Yu, M. Van Buskirk, S. Kawamura, K. Kurihara, H. Kawashima, H. Watanabe","doi":"10.1109/ISSCC.1996.488507","DOIUrl":null,"url":null,"abstract":"An embedded 5 V only 16 M flash memory has an on-chip state machine that generates embedded program and erase algorithms, eliminating system execution of these operations. The system issues a series of commands decoded by the state machine for on-chip execution. It is a /spl times/8 part with a read/busy pin to indicate to the system if the part is in an embedded mode, and a RESETB pin to terminate any operation being executed by the state machine and reset the part to the read mode. Erase is by applying a negative voltage to the control gate of the array and a positive voltage VS to the sector array source.","PeriodicalId":162539,"journal":{"name":"1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC","volume":"55 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1996-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":"{\"title\":\"A 55 ns 0.35 /spl mu/m 5 V-only 16 M flash memory with deep-power-down\",\"authors\":\"B. Venkatesh, M. Chung, S. Govindachar, V. Santurkar, C. Bill, R. Gutala, D. Zhou, J. Yu, M. Van Buskirk, S. Kawamura, K. Kurihara, H. Kawashima, H. Watanabe\",\"doi\":\"10.1109/ISSCC.1996.488507\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"An embedded 5 V only 16 M flash memory has an on-chip state machine that generates embedded program and erase algorithms, eliminating system execution of these operations. The system issues a series of commands decoded by the state machine for on-chip execution. It is a /spl times/8 part with a read/busy pin to indicate to the system if the part is in an embedded mode, and a RESETB pin to terminate any operation being executed by the state machine and reset the part to the read mode. Erase is by applying a negative voltage to the control gate of the array and a positive voltage VS to the sector array source.\",\"PeriodicalId\":162539,\"journal\":{\"name\":\"1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC\",\"volume\":\"55 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1996-02-08\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"7\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISSCC.1996.488507\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.1996.488507","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 55 ns 0.35 /spl mu/m 5 V-only 16 M flash memory with deep-power-down
An embedded 5 V only 16 M flash memory has an on-chip state machine that generates embedded program and erase algorithms, eliminating system execution of these operations. The system issues a series of commands decoded by the state machine for on-chip execution. It is a /spl times/8 part with a read/busy pin to indicate to the system if the part is in an embedded mode, and a RESETB pin to terminate any operation being executed by the state machine and reset the part to the read mode. Erase is by applying a negative voltage to the control gate of the array and a positive voltage VS to the sector array source.