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1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC最新文献

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0.25 /spl mu/m CMOS/SIMOX gate array LSI 0.25 /spl mu/m CMOS/SIMOX门阵列LSI
1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC Pub Date : 1996-02-08 DOI: 10.1109/ISSCC.1996.488525
M. Ino, H. Sawada, K. Nishimura, M. Urano, H. Suto, S. Date, T. Ishihara, T. Takeda, Y. Kado, H. Inokawa, T. Tsuchiya, Y. Sakakibara, Y. Arita, K. Izumi, K. Takeya, T. Sakai
{"title":"0.25 /spl mu/m CMOS/SIMOX gate array LSI","authors":"M. Ino, H. Sawada, K. Nishimura, M. Urano, H. Suto, S. Date, T. Ishihara, T. Takeda, Y. Kado, H. Inokawa, T. Tsuchiya, Y. Sakakibara, Y. Arita, K. Izumi, K. Takeya, T. Sakai","doi":"10.1109/ISSCC.1996.488525","DOIUrl":"https://doi.org/10.1109/ISSCC.1996.488525","url":null,"abstract":"Silicon-on-insulator (SOI) devices have several advantages. Small parasitic capacitances make them useful for high-speed, low-power and low-voltage LSIs. SOI devices are soft-error free, latchup free, and have a high-density layout due to complete isolation. In this paper, we report a 0.25 /spl mu/m CMOS/SIMOX 300 kG gate array LSI using fully-depleted MOSFETs fabricated on a low-dose high-quality SIMOX substrate.","PeriodicalId":162539,"journal":{"name":"1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131910176","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A complete AM/FM stereo receiver and tuning system on a single chip 一个完整的调幅/调频立体声接收机和调谐系统在一个单一的芯片
1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC Pub Date : 1996-02-08 DOI: 10.1109/ISSCC.1996.488595
K. Kianush
{"title":"A complete AM/FM stereo receiver and tuning system on a single chip","authors":"K. Kianush","doi":"10.1109/ISSCC.1996.488595","DOIUrl":"https://doi.org/10.1109/ISSCC.1996.488595","url":null,"abstract":"The electronic tuning delegates part of the tuning to the receiver and uses a standby mode to reduce power consumption and avoid interference with sensitive RF parts, facilitating integration of the receiver and the tuning system on one IC. To achieve a high degree of integration, the tuning system and local controller are integrated with the receiver. The local controller carries out the tuning operations, with simple commands from the microcontroller. This IC is referred to as a self-tuned receiver (STR).","PeriodicalId":162539,"journal":{"name":"1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC","volume":"84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132201233","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A 4.3 ns 0.3 /spl mu/m CMOS 54/spl times/54 b multiplier using precharged pass-transistor logic 一个4.3 ns 0.3 /spl mu/m CMOS 54/spl倍/ 54b乘法器，采用预充电通管逻辑
1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC Pub Date : 1996-02-08 DOI: 10.1109/ISSCC.1996.488719
M. Hanawa, K. Kaneko, T. Kawashimo, H. Maruyama
{"title":"A 4.3 ns 0.3 /spl mu/m CMOS 54/spl times/54 b multiplier using precharged pass-transistor logic","authors":"M. Hanawa, K. Kaneko, T. Kawashimo, H. Maruyama","doi":"10.1109/ISSCC.1996.488719","DOIUrl":"https://doi.org/10.1109/ISSCC.1996.488719","url":null,"abstract":"A 54/spl times/54 b multiplier with 4.3 ns latency at 2.5 V supply and a 16.96 mm/sup 2/ active area is implemented in 0.3 /spl mu/m CMOS with 6.5 nm gate oxide and four-layer metal. This 4.3 ns latency multiplier is for a floating-point unit (FPU) on a CMOS RISC processor capable of performing IEEE double precision multiply operations in three pipelined stages at 400 MHz (7.5 ns latency and 2.5 ns throughput). This multiplier consists of a 54/spl times/54 b carry-save adder tree and a 108 b carry propagation adder. This multiplier achieves 4.3 ns performance using a modified Wallace tree implemented from 4:2 compressors with precharged pass-transistor circuits, radix-2 Booth encoding with an unbalanced buffer for generating select signals, and a short-path carry-lookahead adder.","PeriodicalId":162539,"journal":{"name":"1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC","volume":"os-26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127863020","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
A 1.8 V 94 dB dynamic range /spl Sigma//spl Delta/ modulator for voice applications 1.8 V 94 dB动态范围/spl Sigma//spl Delta/调制器用于语音应用
1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC Pub Date : 1996-02-08 DOI: 10.1109/ISSCC.1996.488583
E. MacRobbie, R. Halim, G. Temes
{"title":"A 1.8 V 94 dB dynamic range /spl Sigma//spl Delta/ modulator for voice applications","authors":"E. MacRobbie, R. Halim, G. Temes","doi":"10.1109/ISSCC.1996.488583","DOIUrl":"https://doi.org/10.1109/ISSCC.1996.488583","url":null,"abstract":"This 2nd-order switched-capacitor (SC) /spl Sigma//spl Delta/ modulator uses a 1.8 V power supply. The circuit provides 15 b S/N performance over the 300 Hz-3.5 kHz band and hence has application in voice codecs. The circuit is designed for a nominal S/N performance of 16 b.","PeriodicalId":162539,"journal":{"name":"1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127984077","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
2.8 Gb/s 176 mW byte-interleaved and 3.0 Gb/s 118 mW bit-interleaved 8:1 multiplexers 2.8 Gb/s 176 mW字节交错和3.0 Gb/s 118 mW位交错8:1多路复用器
1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC Pub Date : 1996-02-08 DOI: 10.1109/ISSCC.1996.488536
M. Kurisu, M. Kaneko, T. Suzaki, A. Tanabe, M. Togo, A. Furukawa, T. Tamura, Ken Nakajima, Kazuyoshi Yoshida
{"title":"2.8 Gb/s 176 mW byte-interleaved and 3.0 Gb/s 118 mW bit-interleaved 8:1 multiplexers","authors":"M. Kurisu, M. Kaneko, T. Suzaki, A. Tanabe, M. Togo, A. Furukawa, T. Tamura, Ken Nakajima, Kazuyoshi Yoshida","doi":"10.1109/ISSCC.1996.488536","DOIUrl":"https://doi.org/10.1109/ISSCC.1996.488536","url":null,"abstract":"2.8 Gbps/176 mW byte-interleaved and 3.0 Gbps/l18 mW bit-interleaved 8:1 multiplexers use 0.15 /spl mu/m CMOS technology. A byte-interleaving scheme divides input-registers into two symmetrical matrices to realize a high-density layout. Both chips have the same 8:1 time-division multiplexing core with a static shift-register architecture. The critical path delay is reduced by introducing dual-outputs D-FFs for the shift-registers. Bit-clock and byte-clock are precisely distributed to maximize speed. Direct interface with ECL circuits uses a negative supply of -2 V (VTT) and high-speed I/O buffers.","PeriodicalId":162539,"journal":{"name":"1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116605530","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 25
128 Mb/s multiport CMOS binary active-pixel image sensor 128 Mb/s多端口CMOS二进制有源像素图像传感器
1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC Pub Date : 1996-02-08 DOI: 10.1109/ISSCC.1996.488531
R. Panicacci, S. Kemeny, P.D. Jones, C. Staller, E. Fossum
{"title":"128 Mb/s multiport CMOS binary active-pixel image sensor","authors":"R. Panicacci, S. Kemeny, P.D. Jones, C. Staller, E. Fossum","doi":"10.1109/ISSCC.1996.488531","DOIUrl":"https://doi.org/10.1109/ISSCC.1996.488531","url":null,"abstract":"A 128/spl times/128 photo-diode active pixel sensor (APS) with an on-chip array sequencing controller and 1b thresholding circuitry processes 8,192-frames/s at a 128 Mb data rate onto a 8 b wide parallel-digital output port. In addition, the on-chip controller can be commanded to output data through either a serial digital port for lower bandwidth requirements or through a serial analog port for higher-resolution off-chip analog-to-digital conversion.","PeriodicalId":162539,"journal":{"name":"1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114447327","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
High temperature electronics using silicon technology 高温电子采用硅技术
1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC Pub Date : 1996-02-08 DOI: 10.1109/ISSCC.1996.488735
F. Trofimenkoff, I. Finvers, R. Smallwood
{"title":"High temperature electronics using silicon technology","authors":"F. Trofimenkoff, I. Finvers, R. Smallwood","doi":"10.1109/ISSCC.1996.488735","DOIUrl":"https://doi.org/10.1109/ISSCC.1996.488735","url":null,"abstract":"In this paper, techniques used to realize precision CMOS circuits for use in down-hole oil and gas field applications are described. The focus is on bulk CMOS circuits so that complete mixed analog/digital precision monolithic data acquisition systems can be fabricated in a standard 5 V digital process. Successful designs to date include an A/D converter with 15 b absolute accuracy at 175/spl deg/C in 3 /spl mu/m CMOS, an autozeroed op amp with low-offset voltage and current at 200/spl deg/C in 1.2 /spl mu/m CMOS, and a high-resolution A/D system for resistance bridge transducers incorporating input offset voltage and bias current error suppression in 1.2 /spl mu/m CMOS.","PeriodicalId":162539,"journal":{"name":"1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130258470","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
A two-chip digital car radio 一个双芯片数字车载收音机
1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC Pub Date : 1996-02-08 DOI: 10.1109/ISSCC.1996.488713
L. Vogt, D. Brookshire, S. Lottholz, G. Zwiehoff
{"title":"A two-chip digital car radio","authors":"L. Vogt, D. Brookshire, S. Lottholz, G. Zwiehoff","doi":"10.1109/ISSCC.1996.488713","DOIUrl":"https://doi.org/10.1109/ISSCC.1996.488713","url":null,"abstract":"Car radio design has been dominated for years by analog signal processing. If digital signal processing is used in a car radio, it begins with the multiplex signal (audio frequency) where filtering and sound control gives new features to the radio. The concept of the two chip digital car radio goes beyond these features: digitization of the intermediate frequency (IF); and mixed-signal processing technology using embedded DSP coprocessors.","PeriodicalId":162539,"journal":{"name":"1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116121144","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 23
A 200 MHz 9-tap analog equalizer for magnetic disk read channels in 0.6 /spl mu/m CMOS 一个200 MHz 9分路模拟均衡器，用于0.6 /spl mu/m CMOS的磁盘读通道
1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC Pub Date : 1996-02-08 DOI: 10.1109/ISSCC.1996.488520
Danfeng Xu, Yonghua Song, G. T. Uehara
{"title":"A 200 MHz 9-tap analog equalizer for magnetic disk read channels in 0.6 /spl mu/m CMOS","authors":"Danfeng Xu, Yonghua Song, G. T. Uehara","doi":"10.1109/ISSCC.1996.488520","DOIUrl":"https://doi.org/10.1109/ISSCC.1996.488520","url":null,"abstract":"This paper describes an analog discrete-time equalizer that uses switched-capacitor (SC) filtering capable of achieving speeds higher than can otherwise be attained using conventional opamp techniques. The approach employs parallelism and exclusive use of open-loop circuitry in the signal path. Conventional SC filters require technologies with high-quality capacitors to create accurate ratios. The approach eliminates high-quality capacitors in the signal path and is amenable to digital CMOS processes.","PeriodicalId":162539,"journal":{"name":"1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116939412","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 26
A 200 Mb/s PRML read/write channel IC 一个200mb /s的PRML读写通道IC
1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC Pub Date : 1996-02-08 DOI: 10.1109/ISSCC.1996.488516
K. Parsi, R. Burns, A. Chaiken, M. Chambers, R. Cheung, B. Forni, D. Harnishfeger, C. Jam, S. Kaylor, M. Pennell, J. Perez, M. Rohrbaugh, M. Ross, G. Stuhlmiller, N. Weiner
{"title":"A 200 Mb/s PRML read/write channel IC","authors":"K. Parsi, R. Burns, A. Chaiken, M. Chambers, R. Cheung, B. Forni, D. Harnishfeger, C. Jam, S. Kaylor, M. Pennell, J. Perez, M. Rohrbaugh, M. Ross, G. Stuhlmiller, N. Weiner","doi":"10.1109/ISSCC.1996.488516","DOIUrl":"https://doi.org/10.1109/ISSCC.1996.488516","url":null,"abstract":"The hard disk drive industry is looking at synchronous design techniques (PRML) with a view to increasing storage density. Currently the high performance commercial read/write channels use (0, 4/4) codes to achieve up to 120 Mb/s data transfer rates. This paper describes a fully integrated read/write channel IC that operates at over 200 Mb/s. The single-chip solution in 0.51 /spl mu/m BiCMOS, has 20 mm/sup 2/ die and uses 0.85 W at 200 Mb/s.","PeriodicalId":162539,"journal":{"name":"1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121672520","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
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