0.25 /spl mu/m CMOS/SIMOX gate array LSI

1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC Pub Date : 1996-02-08 DOI:10.1109/ISSCC.1996.488525

M. Ino, H. Sawada, K. Nishimura, M. Urano, H. Suto, S. Date, T. Ishihara, T. Takeda, Y. Kado, H. Inokawa, T. Tsuchiya, Y. Sakakibara, Y. Arita, K. Izumi, K. Takeya, T. Sakai

引用次数: 7

Abstract

Silicon-on-insulator (SOI) devices have several advantages. Small parasitic capacitances make them useful for high-speed, low-power and low-voltage LSIs. SOI devices are soft-error free, latchup free, and have a high-density layout due to complete isolation. In this paper, we report a 0.25 /spl mu/m CMOS/SIMOX 300 kG gate array LSI using fully-depleted MOSFETs fabricated on a low-dose high-quality SIMOX substrate.

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0.25 /spl mu/m CMOS/SIMOX门阵列LSI

绝缘体上硅(SOI)器件有几个优点。小的寄生电容使它们适用于高速、低功率和低电压的lsi。SOI器件无软误差，无闭锁，并且由于完全隔离而具有高密度布局。在本文中，我们报道了一个0.25 /spl μ l /m CMOS/SIMOX 300 kG栅极阵列LSI，使用在低剂量高质量SIMOX衬底上制造的全耗尽mosfet。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC

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