A 4.3 ns 0.3 /spl mu/m CMOS 54/spl times/54 b multiplier using precharged pass-transistor logic

Abstract

A 54/spl times/54 b multiplier with 4.3 ns latency at 2.5 V supply and a 16.96 mm/sup 2/ active area is implemented in 0.3 /spl mu/m CMOS with 6.5 nm gate oxide and four-layer metal. This 4.3 ns latency multiplier is for a floating-point unit (FPU) on a CMOS RISC processor capable of performing IEEE double precision multiply operations in three pipelined stages at 400 MHz (7.5 ns latency and 2.5 ns throughput). This multiplier consists of a 54/spl times/54 b carry-save adder tree and a 108 b carry propagation adder. This multiplier achieves 4.3 ns performance using a modified Wallace tree implemented from 4:2 compressors with precharged pass-transistor circuits, radix-2 Booth encoding with an unbalanced buffer for generating select signals, and a short-path carry-lookahead adder.