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1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC最新文献

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A 200 Mb/s analog DFE read channel 一个200mb /s的模拟DFE读通道
1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC Pub Date : 1996-02-08 DOI: 10.1109/ISSCC.1996.488519
N. Sands, M. Hauser, G. Liang, G. Groenewold, S. Lam, Chao-Ho Lin, J. Kuklewicz, L. Lang, R. Dakshinamurthy
{"title":"A 200 Mb/s analog DFE read channel","authors":"N. Sands, M. Hauser, G. Liang, G. Groenewold, S. Lam, Chao-Ho Lin, J. Kuklewicz, L. Lang, R. Dakshinamurthy","doi":"10.1109/ISSCC.1996.488519","DOIUrl":"https://doi.org/10.1109/ISSCC.1996.488519","url":null,"abstract":"A 200 Mb/s read-channel IC realizes an enhanced decision-feedback equalizer (DFE) with a combination of continuous and discrete time analog and digital signal processing. The design uses a 20 GHz peak-f/sub T/, BiCMOS process operating at 5 V, with a power consumption of approximately 700 mW. All associated functions are included: bit detection, RLL encoder/decoder, servo demodulation, and write precompensation. Data rate range is 64200 Mb/s at a normalized recording density of 1.8-2.4.","PeriodicalId":162539,"journal":{"name":"1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC","volume":"51 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115978783","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 24
A millimeter-wave flip-chip IC using micro-bump bonding technology 采用微碰撞键合技术的毫米波倒装集成电路
1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC Pub Date : 1996-02-08 DOI: 10.1109/ISSCC.1996.488738
H. Sakai, Y. Ota, K. Inoue, M. Yanagihara, T. Matsuno, M. Tanabe, T. Yoshida, Y. Ikeda, S. Fujita, K. Takahashi, M. Sagawa
{"title":"A millimeter-wave flip-chip IC using micro-bump bonding technology","authors":"H. Sakai, Y. Ota, K. Inoue, M. Yanagihara, T. Matsuno, M. Tanabe, T. Yoshida, Y. Ikeda, S. Fujita, K. Takahashi, M. Sagawa","doi":"10.1109/ISSCC.1996.488738","DOIUrl":"https://doi.org/10.1109/ISSCC.1996.488738","url":null,"abstract":"This millimeter-wave flip-chip IC (MFIC) is a compact hybrid constructed by bonding a mm-wave transistor or its IC chips upside down on thin film microstrip lines formed on a Si substrate. Production costs of this IC are expected to be drastically reduced compared with those of the conventional MMIC because the passive elements, which usually occupy large chip area, are formed not on the expensive heterostructure substrate, but on the low-cost Si substrate. Moreover, design flexibility such as a device choice and integration is expanded including the integration of antennas. Using 9 /spl mu/m-thick p-CVD SiO/sub 2/ as a dielectric film, microstrip lines on Si substrate were realized. Using MBB technology to fabricate K-band MFIC amplifiers demonstrates the MFIC concept.","PeriodicalId":162539,"journal":{"name":"1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128658917","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
0.5 V SOI CMOS pass-gate logic 0.5 V SOI CMOS通栅逻辑
1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC Pub Date : 1996-02-08 DOI: 10.1109/ISSCC.1996.488526
T. Fuse, Y. Oowaki, M. Terauchi, S. Watanabe, M. Yoshimi, K. Ohuchi, J. Matsunaga
{"title":"0.5 V SOI CMOS pass-gate logic","authors":"T. Fuse, Y. Oowaki, M. Terauchi, S. Watanabe, M. Yoshimi, K. Ohuchi, J. Matsunaga","doi":"10.1109/ISSCC.1996.488526","DOIUrl":"https://doi.org/10.1109/ISSCC.1996.488526","url":null,"abstract":"Demand for low-power ULSIs for mobile electronic equipment is increasing rapidly. To reduce power consumption, lower operating voltage and minimized device size (or count) is essential. To lower the actual threshold voltage and lower the operation voltage, SOI MOSFET with gate-body connection is proposed. However, the circuit architecture that affords the maximum advantage of the body controlled SOI MOSFET has not yet been reported. The SOI CMOS pass-gate logic described here offers the lowest operation voltage and reduced transistor dimensions. In this logic the body of the SOI pass-gate is connected to the input signal given to the gate. Low threshold voltage for the onstate pass-gate and high threshold voltage for the off-state passgate is realized, and the increase in the threshold voltage due to the body-effect is suppressed. Two types of buffer suitable for SOI pass-gate logic are examined.","PeriodicalId":162539,"journal":{"name":"1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126427549","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
A 1 Mb 5-transistor/bit non-volatile CAM based on flash-memory technologies 基于闪存技术的1mb 5晶体管/位非易失性CAM
1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC Pub Date : 1996-02-08 DOI: 10.1109/ISSCC.1996.488505
T. Miwa, H. Yamada, Y. Hirota, T. Satoh, H. Hara
{"title":"A 1 Mb 5-transistor/bit non-volatile CAM based on flash-memory technologies","authors":"T. Miwa, H. Yamada, Y. Hirota, T. Satoh, H. Hara","doi":"10.1109/ISSCC.1996.488505","DOIUrl":"https://doi.org/10.1109/ISSCC.1996.488505","url":null,"abstract":"A 1 Mb content-addressable memory LSI based on flash technologies (flash CAM) has memory cells consisting of a pair of flash memory cell transistors. 10.34 /spl mu/m/sup 2/ cell and 42.9mm/sup 2/ die are attained with 0.8 /spl mu/m design rules. The flash CAM can be searched for masked binary data. Read access time and search access time are 115 ns and 145 ns, respectively, with a 5 V supply voltage. Power dissipation is 200 mW at 3.3 MHz. The flash CAM cell consists of two floating-gate transistors. This structure is in strong contrast to the comparator-added-storage structure of 17-transistor SRAM-based cells or five-transistor two-capacitor of DRAM-based cells. In addition to non-volatility, flash CAMs also feature on-board programmable/erasable memory.","PeriodicalId":162539,"journal":{"name":"1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127496426","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A 143-360 Mb/s auto-rate selecting data-retimer chip for serial-digital video signals 一种用于串行数字视频信号的143- 360mb /s自动选择数据定时器芯片
1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC Pub Date : 1996-02-08 DOI: 10.1109/ISSCC.1996.488568
D. Potson, A. Buchholz
{"title":"A 143-360 Mb/s auto-rate selecting data-retimer chip for serial-digital video signals","authors":"D. Potson, A. Buchholz","doi":"10.1109/ISSCC.1996.488568","DOIUrl":"https://doi.org/10.1109/ISSCC.1996.488568","url":null,"abstract":"Current serial digital video retimers have two limitations: (1) manufacturers are required to incorporate PCB adjustments for center frequency at each rate, and (2) auto rate selection (ARS) uses complex circuitry unnecessary for purely signal-routing applications. This circuitry, which relies on the successful detection of a de-scrambled 30 b word, operates at the clock rate and increases power dissipation. The retimer described here addresses these problems by (1) wafer trim to eliminate PCB tweaks, and (2) a simplified implementation of ARS.","PeriodicalId":162539,"journal":{"name":"1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116706472","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A 200 MHz 256 kB second level cache with 1.6 GB/s data bandwidth 200mhz 256kb二级缓存，数据带宽1.6 GB/s
1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC Pub Date : 1996-02-08 DOI: 10.1109/ISSCC.1996.488552
D. DiMarco, M. Balmer, C. Freeman, K. Hose, J.L. Miller, E. Riggs
{"title":"A 200 MHz 256 kB second level cache with 1.6 GB/s data bandwidth","authors":"D. DiMarco, M. Balmer, C. Freeman, K. Hose, J.L. Miller, E. Riggs","doi":"10.1109/ISSCC.1996.488552","DOIUrl":"https://doi.org/10.1109/ISSCC.1996.488552","url":null,"abstract":"Improvements in processor performance have given rise to tightly-coupled, high-bandwidth second-level caches that are key to processor performance. This paper describes a 256 kB, 4-way set-associative companion cache SRAM to a microprocessor. High speed is achieved by keeping the processor and cache in the same 2-chip module and by communicating over a private 72 b data bus. Supply voltage is 3.3 V and maximum power is 3.8 W at 150 MHz, assuming back-to-back reads. The BiCMOS process features 4-level metal and 0.4 /spl mu/m Leff.","PeriodicalId":162539,"journal":{"name":"1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121897566","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A 150 Mb/s PRML chip for magnetic disk drives 用于磁盘驱动器的150 Mb/s的PRML芯片
1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC Pub Date : 1996-02-08 DOI: 10.1109/ISSCC.1996.488514
Naoki Sato, S. Mita, T. Takashi
{"title":"A 150 Mb/s PRML chip for magnetic disk drives","authors":"Naoki Sato, S. Mita, T. Takashi","doi":"10.1109/ISSCC.1996.488514","DOIUrl":"https://doi.org/10.1109/ISSCC.1996.488514","url":null,"abstract":"Recent magnetic disk drives require high transfer rates and recording densities. PRML signaling is now prevalent in digital read/write channels. This PRML chip operates at a maximum data rate of 150 Mb/s with 1550 mW and includes all basic functions such as servo demodulation and write pre-compensation for magnetic disk drives with optimized circuit size. The chip is fabricated in 0.7 /spl mu/m double-poly double-metal BICMOS suitable for low-power devices and is packed in a 100-pin quad flat package with a die approximately 7 mm/sup 2/. This chip has a single 5 V power supply.","PeriodicalId":162539,"journal":{"name":"1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114355220","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 22
Complementary adiabatic and fully adiabatic MOS logic families for gigascale integration 用于千兆级集成的互补绝热和完全绝热MOS逻辑家族
1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC Pub Date : 1996-02-08 DOI: 10.1109/ISSCC.1996.488626
V. De, J. Meindl
{"title":"Complementary adiabatic and fully adiabatic MOS logic families for gigascale integration","authors":"V. De, J. Meindl","doi":"10.1109/ISSCC.1996.488626","DOIUrl":"https://doi.org/10.1109/ISSCC.1996.488626","url":null,"abstract":"A fundamental opportunity for adiabatic-reversible computation is prescribed by the second law of thermodynamics through the universal relationship between entropy and heat generation in a closed system. The complementary adiabatic MOS (CAMOS) and fully adiabatic MOS (ADMOS) logic families provide practical circuit implementations of quasi-adiabatic and quasi-adiabatic-reversible computing, respectively, and offer promising alternatives to CMOS logic for low-power GSI systems.","PeriodicalId":162539,"journal":{"name":"1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC","volume":"150 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117321080","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 24
A multimedia-enhanced x86 processor 多媒体增强的x86处理器
1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC Pub Date : 1996-02-08 DOI: 10.1109/ISSCC.1996.488579
F. Norrod, R. Wawrzynek
{"title":"A multimedia-enhanced x86 processor","authors":"F. Norrod, R. Wawrzynek","doi":"10.1109/ISSCC.1996.488579","DOIUrl":"https://doi.org/10.1109/ISSCC.1996.488579","url":null,"abstract":"This x86 compatible CPU with multimedia functionality includes DRAM controller, accelerated graphics controller, and PCI bus interface. The integer pipeline and L1 cache of the CPU are enhanced to accelerate graphics and multimedia applications, and take advantage of the on-chip peripherals. Modules integrated onto the die are chosen because they are high-value functions with compelling performance or reduced complexity when integrated with the CPU. Graphics and video functions benefit from a tight integration with the CPU since partitioning of functions between hardware and software can differ from a traditional architecture without hurting performance.","PeriodicalId":162539,"journal":{"name":"1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134497180","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
350 MHz time-multiplexed 8-port SRAM and word size variable multiplier for multimedia DSP 350mhz时复用8端口SRAM和字长可变乘法器的多媒体DSP
1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC Pub Date : 1996-02-08 DOI: 10.1109/ISSCC.1996.488548
T. Takayanagi, K. Nogami, F. Hatori, N. Hatanaka, M. Takahashi, M. Ichida, S. Kitabayashi, T. Higashi, M. Klein, J. Thomson, R. Carpenter, R. Donthi, D. Renfrow, J. Zheng, L. Tinkey, B. Maness, J. Battle, S. Purcell, T. Sakurai
{"title":"350 MHz time-multiplexed 8-port SRAM and word size variable multiplier for multimedia DSP","authors":"T. Takayanagi, K. Nogami, F. Hatori, N. Hatanaka, M. Takahashi, M. Ichida, S. Kitabayashi, T. Higashi, M. Klein, J. Thomson, R. Carpenter, R. Donthi, D. Renfrow, J. Zheng, L. Tinkey, B. Maness, J. Battle, S. Purcell, T. Sakurai","doi":"10.1109/ISSCC.1996.488548","DOIUrl":"https://doi.org/10.1109/ISSCC.1996.488548","url":null,"abstract":"A multimedia DSP optimized for digital audio/video applications provides simple flexible cost-effective solution capable of GUI acceleration, MPEG2 decoding, real-time MPEG1 encoding, personal video conferencing, 28.8 kbps fax/modem, and audio/sound functions. The main frequency of the chip is 62.5 MHz and the supply voltage is 3.3 V. The chip is fabricated in 0.5 /spl mu/m triple-metal CMOS, occupies 12.8/spl times/14.0 mm/sup 2/ and is mounted in a 240 QFP package with a heat-spreader. The chip integrates high-performance custom macro blocks: an interface for Rambus DRAMs (RAC), a 37 kb time-multiplexed 8-ported SRAM, 72 b scalable datapath and single oxide 3 V/5 V I/O. The focus here is the SRAM and word-size-variable multiplier.","PeriodicalId":162539,"journal":{"name":"1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131425470","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
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