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1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC最新文献

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A single-chip multimedia audio system with digital sample rate conversion and FM sound synthesis 单片机多媒体音频系统的数字采样率转换和FM声音合成
1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC Pub Date : 1996-02-08 DOI: 10.1109/ISSCC.1996.488593
S. Bernadas, M. Alexander, Jieren Bian, Golam Chowdhury, Qiujie Dong, M. Gentry, A. Goyal, M. Jaric, M. Jenkins, M. Kent, R. Malcolm, P. Matthews, K. McLaughlin, Murali Munuswamy, Kartika Prihadi, M. Rovner, J. Scott, Krishnan Subramoniam, W. Wagner, J. Wu
{"title":"A single-chip multimedia audio system with digital sample rate conversion and FM sound synthesis","authors":"S. Bernadas, M. Alexander, Jieren Bian, Golam Chowdhury, Qiujie Dong, M. Gentry, A. Goyal, M. Jaric, M. Jenkins, M. Kent, R. Malcolm, P. Matthews, K. McLaughlin, Murali Munuswamy, Kartika Prihadi, M. Rovner, J. Scott, Krishnan Subramoniam, W. Wagner, J. Wu","doi":"10.1109/ISSCC.1996.488593","DOIUrl":"https://doi.org/10.1109/ISSCC.1996.488593","url":null,"abstract":"This paper describes on-chip digital mixing and digital sample rate conversion used to perform mixing for multimedia applications. Digital sample rate conversion facilitates future integration of new features such as wavetable sound synthesis and 3D sound effects processing, while reducing integration time and digital testing costs compared to traditional analog techniques.","PeriodicalId":162539,"journal":{"name":"1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128567169","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A 130 Mb/s PRML read/write channel with digital-servo detection 一个130 Mb/s的PRML读/写通道与数字伺服检测
1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC Pub Date : 1996-02-08 DOI: 10.1109/ISSCC.1996.488515
G. Tuttle, G. Vishakhadatta, M. Goldenberg, D. Kuai, L. Mehr, A. Singh, R. Trujillo, D. Welland, R. Gomez, F. Aram, J. Hein, D. Reed, J. Mitchem, W. Bliss, A. Armstrong, R. Behrens, T. Dudley, C. Duey, J. Meadows, W. Foland, R. W. Hull, D. P. Turner
{"title":"A 130 Mb/s PRML read/write channel with digital-servo detection","authors":"G. Tuttle, G. Vishakhadatta, M. Goldenberg, D. Kuai, L. Mehr, A. Singh, R. Trujillo, D. Welland, R. Gomez, F. Aram, J. Hein, D. Reed, J. Mitchem, W. Bliss, A. Armstrong, R. Behrens, T. Dudley, C. Duey, J. Meadows, W. Foland, R. W. Hull, D. P. Turner","doi":"10.1109/ISSCC.1996.488515","DOIUrl":"https://doi.org/10.1109/ISSCC.1996.488515","url":null,"abstract":"The detection of servo information in hard disk drive read channels has traditionally been implemented with analog circuits and converted with an off-chip analog-to-digital converter (ADC). The benefits of digital servo detection include system cost savings through the elimination of the off-chip ADC, reduced development time, repeatability, testability, and ease of future integration. The full digital PRML chip is described.","PeriodicalId":162539,"journal":{"name":"1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC","volume":"287 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116371538","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 27
Serial networks for computing applications 用于计算应用的串行网络
1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC Pub Date : 1996-02-08 DOI: 10.1109/ISSCC.1996.488734
R. Marbot, P. Couteaux, Jean-Claude Lebihan, A. Pierre-Duplessix
{"title":"Serial networks for computing applications","authors":"R. Marbot, P. Couteaux, Jean-Claude Lebihan, A. Pierre-Duplessix","doi":"10.1109/ISSCC.1996.488734","DOIUrl":"https://doi.org/10.1109/ISSCC.1996.488734","url":null,"abstract":"Serial links (i.e., communication paths on single lines, in that the clock information is merged into the data bit stream) have been widely used by the telecom industry since their origin, but the computer community is still very reluctant to introduce them. Transputers pioneered their use in computing applications. However, many system architects still consider serial links as a unreliable communication medium, due to the error rates that they generate in noisy telecom applications. Recent work has demonstrated that serial links display robustness similar to busses, when used in a protected environment. This paper lists the existing serial link technologies in the gigabit per second rates.","PeriodicalId":162539,"journal":{"name":"1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC","volume":"423 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116564336","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 320 MHz, 1.5 mW at 1.35 V CMOS PLL for microprocessor clock generation 320mhz, 1.5 mW, 1.35 V CMOS锁相环，用于微处理器时钟生成
1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC Pub Date : 1996-02-08 DOI: 10.1109/ISSCC.1996.488540
V. V. Kaenel, D. Aebischer, C. Piguet, E. Dijkstra
{"title":"A 320 MHz, 1.5 mW at 1.35 V CMOS PLL for microprocessor clock generation","authors":"V. V. Kaenel, D. Aebischer, C. Piguet, E. Dijkstra","doi":"10.1109/ISSCC.1996.488540","DOIUrl":"https://doi.org/10.1109/ISSCC.1996.488540","url":null,"abstract":"This paper reports on the design of a phase-locked-loop (PLL) for on-chip clock generation for a high-performance microprocessor (/spl mu/P). The power consumption of the /spl mu/P has been reduced by scaling down the supply voltage. The whole system has been implemented using a 0.35/spl mu/m CMOS process that features low-threshold voltages for MOS devices to maintain the speed performance. The /spl mu/P can be set in idle mode to further reduce the overall power consumption. To allow fast recovery from the /spl mu/P idle mode, the PLL runs continuously during this mode. Therefore, the power consumption of the PLL has to be minimized. To obtain the highest performance from the /spl mu/P, the output jitter of the PLL has to be as low as possible. The power switching noise generated by the running /spl mu/P directly affects the output jitter of the on-chip PLL. In summary, the challenge was to design a PLL which combines limited jitter, low-supply voltage and low-power consumption.","PeriodicalId":162539,"journal":{"name":"1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131923992","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 105
Monolithic low-power 16 b 1 MSample/s self-calibrating pipeline ADC 单片低功耗16b1msample /s自校准流水线ADC
1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC Pub Date : 1996-02-08 DOI: 10.1109/ISSCC.1996.488632
M. Mayes, S. Chin
{"title":"Monolithic low-power 16 b 1 MSample/s self-calibrating pipeline ADC","authors":"M. Mayes, S. Chin","doi":"10.1109/ISSCC.1996.488632","DOIUrl":"https://doi.org/10.1109/ISSCC.1996.488632","url":null,"abstract":"Pipelined architectures enable the implementation of high-speed, high-resolution, low-power analog-to-digital converters (ADCs). Concurrent processing of analog signals results in power and/or speed advantages over flash and multistep ADC architectures. While self-calibration techniques reduce the effects of component mismatches, the digital crosstalk due to correction circuitry can degrade the noise and linearity performance of the overall converter. Previous pipeline ADCs achieve high speed and high resolution, but with the digital circuitry off chip. This 16 b 1 MSample/s pipeline ADC with on-chip digital correction circuitry operates on a single SV analog supply. Problems due to digital crosstalk and solutions reducing its effects are presented. Reduction of integral non-linearity (INL) errors due to capacitor voltage coefficient are discussed.","PeriodicalId":162539,"journal":{"name":"1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128015962","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
A 56-entry instruction reorder buffer 一个包含56个条目的指令重排序缓冲区
1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC Pub Date : 1996-02-08 DOI: 10.1109/ISSCC.1996.488575
N.B. Gaddis, J. R. Butler, A. Kumar, W. J. Queen
{"title":"A 56-entry instruction reorder buffer","authors":"N.B. Gaddis, J. R. Butler, A. Kumar, W. J. Queen","doi":"10.1109/ISSCC.1996.488575","DOIUrl":"https://doi.org/10.1109/ISSCC.1996.488575","url":null,"abstract":"A speculative execution high-end PA-RISC CPU has two 28-entry out-of-order instruction reorder buffers (IRBs), one for alu/floating point operations and one for memory operations. The IRBs are capable of inserting any combination of four instructions per cycle. Each cycle, the IRBs launch up to four instructions for execution, two from the ALU IRB and two from the MEM IRB. Up to four instructions (two from each IRB) retire each cycle. The insert, launch and retire mechanisms of this out-of-order machine contain 850 k transistors in 52.6 mm/sup 2/.","PeriodicalId":162539,"journal":{"name":"1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133092324","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
Intelligent optical backplanes 智能光学背板
1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC Pub Date : 1996-02-08 DOI: 10.1109/ISSCC.1996.488736
H. S. Hinton, K. Devenport, D. Plant, T. Szymanski
{"title":"Intelligent optical backplanes","authors":"H. S. Hinton, K. Devenport, D. Plant, T. Szymanski","doi":"10.1109/ISSCC.1996.488736","DOIUrl":"https://doi.org/10.1109/ISSCC.1996.488736","url":null,"abstract":"One of the practical limiting factors in the development and acceptance of teraflop multiprocessor computing systems (as well as large ATM switching systems) is packaging. Currently large systems, 64 processing nodes and above, can require multiple cabinets to house all their electronic equipment. This low-density packaging not only leads to expensive systems but also suffers from increased latency, skew, and other physical problems that limit overall performance. As thermal management schemes have progressed there is a growing trend to package more electronics into smaller physical volumes. The result is the integration of more processing nodes (PN) per integrated circuit, more PNs per printed circuit board (PCB), and more PCBs per shelf. This necessary hardware compression leads to an interconnect bottleneck at the backplane. One approach to overcome these interconnection limitations of electrical backplanes is to exploit the temporal and spatial bandwidth available with the free-space optical technology. A free-space optical backplane is composed of a large number of optically interconnected smart pixel arrays (SPAs). A smart pixel is an optoelectronic device that combines optical inputs and/or outputs with electronic processing circuitry, and is capable of being integrated into two-dimensional arrays. In an intelligent optical backplane, the SPAs control the flow of information between the PCBs.","PeriodicalId":162539,"journal":{"name":"1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133320139","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A programmable codec signal processor 一个可编程的编解码器信号处理器
1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC Pub Date : 1996-02-08 DOI: 10.1109/ISSCC.1996.488557
S. Norsworthy, L. E. Bays, J. Fischer
{"title":"A programmable codec signal processor","authors":"S. Norsworthy, L. E. Bays, J. Fischer","doi":"10.1109/ISSCC.1996.488557","DOIUrl":"https://doi.org/10.1109/ISSCC.1996.488557","url":null,"abstract":"Delta-sigma (/spl Delta//spl Sigma/) codecs have traditionally been used in audio, speech, and telecommunications. More recently, there have been several commercial introductions of DSPs having an on-chip /spl Delta//spl Sigma/ codec with the shortcoming that they have little flexibility in controlling the decimation and interpolation ratios or filter characteristics. A new architecture is introduced that brings the /spl Delta//spl Sigma/ codec more intimately into the DSP.","PeriodicalId":162539,"journal":{"name":"1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130808108","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Bit-line clamped sensing multiplex and accurate high-voltage generator for 0.25 /spl mu/m flash memories 位线钳位感测多路复用和精确的高压发生器，用于0.25 /spl mu/m闪存
1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC Pub Date : 1996-02-08 DOI: 10.1109/ISSCC.1996.488504
T. Kawahara, T. Kobayashi, Y. Jyouno, S. Saeki, N. Miyamoto, T. Adachi, M. Kato, A. Sato, J. Yugami, H. Kume, K. Kimura
{"title":"Bit-line clamped sensing multiplex and accurate high-voltage generator for 0.25 /spl mu/m flash memories","authors":"T. Kawahara, T. Kobayashi, Y. Jyouno, S. Saeki, N. Miyamoto, T. Adachi, M. Kato, A. Sato, J. Yugami, H. Kume, K. Kimura","doi":"10.1109/ISSCC.1996.488504","DOIUrl":"https://doi.org/10.1109/ISSCC.1996.488504","url":null,"abstract":"A 105.9 mm/sup 2/ 128 Mb experimental chip using 0.25 /spl mu/m technology demonstrates the feasibility of circuits that take advantage of the potential scalability of flash memory cells and an accurate internal voltage generator that operates at 2.5 V Vcc: (1) a layout-pitch-relaxing bit-line clamped sensing multiplex and intermittent-burst data transfer (four phases with 500 ns/20 ns) for a 3F (F=feature size) pitch, and (2) a 5 /spl mu/A dynamic band-gap generator under a boosted voltage using triple-well bipolar transistors and a voltage doubler charge pump, for accurate 10 to 20 V generation.","PeriodicalId":162539,"journal":{"name":"1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121300054","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
A laser-detector-hologram unit with IV amplifiers and built-in micro-mirror 一个激光探测器全息图单元与IV放大器和内置微镜
1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC Pub Date : 1996-02-08 DOI: 10.1109/ISSCC.1996.488640
H. Ishiguro, S. Kamimura, T. Higashii, M. Hirose, A. Ueno, A. Yoshikawa, K. Itoh, M. Yamaguchi
{"title":"A laser-detector-hologram unit with IV amplifiers and built-in micro-mirror","authors":"H. Ishiguro, S. Kamimura, T. Higashii, M. Hirose, A. Ueno, A. Yoshikawa, K. Itoh, M. Yamaguchi","doi":"10.1109/ISSCC.1996.488640","DOIUrl":"https://doi.org/10.1109/ISSCC.1996.488640","url":null,"abstract":"This LDH unit integrated with five bipolar amplifiers and a built-in micro-mirror realizes read-out characteristics corresponding to quad-speed (4x) of a CD-ROM drive. The fact that the output impedance of each IV amplifier is low, results in drastic reduction of stray noise. Simulating the response characteristics of the IV amplifiers determines the most suitable conditions for the LDH unit operating at 4x read-out speed of CD-ROM drive.","PeriodicalId":162539,"journal":{"name":"1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121303273","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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