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1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC最新文献

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Multimedia complex on a chip 芯片上的多媒体复合体
1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC Pub Date : 1996-02-08 DOI: 10.1109/ISSCC.1996.488498
H. Sasaki
{"title":"Multimedia complex on a chip","authors":"H. Sasaki","doi":"10.1109/ISSCC.1996.488498","DOIUrl":"https://doi.org/10.1109/ISSCC.1996.488498","url":null,"abstract":"This paper discusses the solid-state circuit technology needed to integrate a multimedia complex on a chip and open up the multimedia world. The requisites for expansion of multimedia, the relation between digital signal processing and solid-state circuit technology, the outlook for the technology, a view of the multimedia complex in the future, and three design issues are discussed.","PeriodicalId":162539,"journal":{"name":"1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC","volume":"119 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122975516","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 36
5.4 GOPS linear array architecture DSP for video-format conversion 5.4视频格式转换的GOPS线性阵列架构DSP
1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC Pub Date : 1996-02-08 DOI: 10.1109/ISSCC.1996.488594
M. Kurokawa, A. Hashiguchi, K. Nakamura, H. Okuda, K. Aoyama, T. Yamazaki, M. Ohki, M. Soneda, K. Seno, I. Kumata, M. Aikawa, H. Hanaki, S. Iwase
{"title":"5.4 GOPS linear array architecture DSP for video-format conversion","authors":"M. Kurokawa, A. Hashiguchi, K. Nakamura, H. Okuda, K. Aoyama, T. Yamazaki, M. Ohki, M. Soneda, K. Seno, I. Kumata, M. Aikawa, H. Hanaki, S. Iwase","doi":"10.1109/ISSCC.1996.488594","DOIUrl":"https://doi.org/10.1109/ISSCC.1996.488594","url":null,"abstract":"A programmable DSP with linear-array architecture for real-time video processing, including video format conversion, has 4320 SIMD processor elements, has a peak processing rate of 5.4 GOPS, and can be applied to HDTV signals with its 75 MHz peak I/O clock rate. Sufficient programmability is provided to execute video-format conversion, such as image-size conversion (ISC) and Y/C separation, and picture-quality improvement, such as noise reduction and image enhancement.","PeriodicalId":162539,"journal":{"name":"1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116004857","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
A 1/4 inch 330 k square pixel progressive-scan IT-CCD image sensor with submicrometer channel width 1/4英寸330平方像素逐行扫描IT-CCD图像传感器，通道宽度为亚微米
1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC Pub Date : 1996-02-08 DOI: 10.1109/ISSCC.1996.488563
T. Kuroda, Y. Matsuda, K. Ishikawa, K. Tachikawa, M. Masuyama, M. Asaumi, M. Niwayama, T. Yamada, Y. Miyata, N. Niisoe, S. Terakawa
{"title":"A 1/4 inch 330 k square pixel progressive-scan IT-CCD image sensor with submicrometer channel width","authors":"T. Kuroda, Y. Matsuda, K. Ishikawa, K. Tachikawa, M. Masuyama, M. Asaumi, M. Niwayama, T. Yamada, Y. Miyata, N. Niisoe, S. Terakawa","doi":"10.1109/ISSCC.1996.488563","DOIUrl":"https://doi.org/10.1109/ISSCC.1996.488563","url":null,"abstract":"A 1/4 inch IT-CCD with 640 (H)/spl times/480 (V) square pixels is described. In a progressive-scan CCD, the gate area for charge storage during vertical charge transfer decreases to less than half compared with a conventional CCD. The first objective is increased charge handling capability per unit gate area to compensate for the gate area decrease. The second is suppression of narrow and/or short-channel effect that is important in IT-CCD with channel area shrinkage. Two techniques overcome these problems. One is to avoid the decrease of effective channel width due to alignment error in stepper lithography that has a significant influence in a narrow-channel CCD. To this end, pixel design and processing are improved so one mask step for the buried channel determines channel width (regulated by three mask steps in a conventional CCD). The other is improvement of the doping profile.","PeriodicalId":162539,"journal":{"name":"1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132496798","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A 7.68 GIPS 3.84 GB/s 1W parallel image processing RAM integrating a 16 Mb DRAM and 128 processors 7.68 GIPS 3.84 GB/s 1W并行图像处理RAM，集成16mb DRAM和128个处理器
1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC Pub Date : 1996-02-08 DOI: 10.1109/ISSCC.1996.488722
Y. Aimoto, T. Kimura, Y. Yabe, H. Heiuchi, Y. Nakazawa, M. Motomura, T. Koga, Y. Fujita, M. Hamada, T. Tanigawa, H. Nobusawa, K. Koyama
{"title":"A 7.68 GIPS 3.84 GB/s 1W parallel image processing RAM integrating a 16 Mb DRAM and 128 processors","authors":"Y. Aimoto, T. Kimura, Y. Yabe, H. Heiuchi, Y. Nakazawa, M. Motomura, T. Koga, Y. Fujita, M. Hamada, T. Tanigawa, H. Nobusawa, K. Koyama","doi":"10.1109/ISSCC.1996.488722","DOIUrl":"https://doi.org/10.1109/ISSCC.1996.488722","url":null,"abstract":"A parallel image processing RAM (PIP-RAM) integrates a 16 Mb DRAM and 128 processor elements (PEs) on a single chip in 64 Mb DRAM process technology. There are three general design requirements when integrating DRAMs and processors onto a single chip: high-data-rate random access, low-power dissipation, and efficiently synchronized DRAM and processor. The PIP-RAM employs three circuit techniques in response to these requirements: (1) a paged-segmentation accessing (PSA), (2) a clocked low-voltage-swing differential-charge-transfer (CLD), and (3) a multiphase synchronization DRAM control (MSD) that uses a multiple-stage PLL. Large memory capacity and high-data-rate random access achieved by these techniques make the PIP-RAM suitable for image processing of large-scale, full-color pictures.","PeriodicalId":162539,"journal":{"name":"1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC","volume":"221 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125374721","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 31
A multimedia 32 b RISC microprocessor with 16 Mb DRAM 多媒体32b RISC微处理器，16mb DRAM
1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC Pub Date : 1996-02-08 DOI: 10.1109/ISSCC.1996.488577
T. Shimizu, J. Korematu, M. Satou, H. Kondo, S. Iwata, K. Sawai, N. Okumura, K. Ishimi, Y. Nakamoto, M. Kumanoya, K. Dosaka, A. Yamazaki, Y. Ajioka, H. Tsubota, Y. Nunomura, T. Urabe, J. Hinata, K. Saitoh
{"title":"A multimedia 32 b RISC microprocessor with 16 Mb DRAM","authors":"T. Shimizu, J. Korematu, M. Satou, H. Kondo, S. Iwata, K. Sawai, N. Okumura, K. Ishimi, Y. Nakamoto, M. Kumanoya, K. Dosaka, A. Yamazaki, Y. Ajioka, H. Tsubota, Y. Nunomura, T. Urabe, J. Hinata, K. Saitoh","doi":"10.1109/ISSCC.1996.488577","DOIUrl":"https://doi.org/10.1109/ISSCC.1996.488577","url":null,"abstract":"This 32 b microprocessor with on-chip 2 MB DRAM is for multimedia applications that require a low-power embedded microprocessor and large memory. Using a typical 0.45 /spl mu/m DRAM process, double-metal CMOS technology, this chip integrates 17 M transistors in 19.9/spl times/7.7 mm/sup 2/. It consists of a 32 b RISC CPU, a 32 b/spl times/16 b multiply accumulator (MAC), a 2 MB DRAM, a 2 kB cache, an external bus interface unit (BIU), and control units. The CPU, DRAM, cache and BIU are connected with a single 128 b internal bus. At 66 MHz, the bus transfers a 128 b data line between the CPU and the cache in one cycle, and between CPU and DRAM in 5 cycles. The external bus is 16 b wide and operates at 16.67 MHz.","PeriodicalId":162539,"journal":{"name":"1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114794218","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 48
A 0.5 V SIMOX-MTCMOS circuit with 200 ps logic gate 一个带200ps逻辑门的0.5 V SIMOX-MTCMOS电路
1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC Pub Date : 1996-02-08 DOI: 10.1109/ISSCC.1996.488524
T. Douseki, S. Shigematsu, Y. Tanabe, M. Harada, H. Inokawa, T. Tsuchiya
{"title":"A 0.5 V SIMOX-MTCMOS circuit with 200 ps logic gate","authors":"T. Douseki, S. Shigematsu, Y. Tanabe, M. Harada, H. Inokawa, T. Tsuchiya","doi":"10.1109/ISSCC.1996.488524","DOIUrl":"https://doi.org/10.1109/ISSCC.1996.488524","url":null,"abstract":"Multi-threshold CMOS (MTCMOS) circuit technology combining low-Vth CMOS logic gates and high-Vth MOSFETs is suitable for 1 V LSIs for battery-operated portable equipment. Improvements in MTCMOS device technology promise to lead to higher operating frequencies. However, higher frequencies will increase power consumption even if the supply voltage is 1 V. To reduce the power consumption, it is necessary to lower the supply voltage below 1 V, without sacrificing speed. A circuit consisting of depletion-mode MOSFETs operates with 200 mV supply. However, it cannot be applied to an LSI with more than 1 k gates because active-mode leakage current is too large. In addition, the circuit needs backgate bias, which is much larger than the supply voltage, to increase the threshold voltage and to reduce the leakage current in the sleep mode. To generate the large back-gate bias, multiple supply voltages or a boost circuit are required. The proposed low supply-voltage MTCMOS circuit with SIMOX technology uses enhancement-mode MOSFFTs and contains no boost circuit. High-speed operation of this SIMOX-MTCMOS circuit at 0.5 V supply is obtained by use of low-Vth CMOS logic gates consisting of fully-depleted body-floating MOSFETs.","PeriodicalId":162539,"journal":{"name":"1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122021206","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 41
A chip-set enabling B-ISDN ATM UNI transmission convergence (TC) AAL 3/4-layers, and ATM layer functions B-ISDN ATM UNI传输汇聚(TC) AAL 3/4层和ATM层功能的芯片组
1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC Pub Date : 1996-02-08 DOI: 10.1109/ISSCC.1996.488533
J. Calderon, J.M. Tapia, L. París
{"title":"A chip-set enabling B-ISDN ATM UNI transmission convergence (TC) AAL 3/4-layers, and ATM layer functions","authors":"J. Calderon, J.M. Tapia, L. París","doi":"10.1109/ISSCC.1996.488533","DOIUrl":"https://doi.org/10.1109/ISSCC.1996.488533","url":null,"abstract":"An internet-working unit called UNICORN is used to interconnect LANs such as Ethernet and MANs such as DQDB over a SDH-based ATM network carrying data at 155Mb/s. Two monolithic B-ISDN ICs perform the critical ATM functions: the TCS chip and the ATM-AAL chip.","PeriodicalId":162539,"journal":{"name":"1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116890238","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 400 MHz 4.5 Mb synchronous BiCMOS SRAM with alternating bit-line loads 具有交替位线负载的400 MHz 4.5 Mb同步BiCMOS SRAM
1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC Pub Date : 1996-02-08 DOI: 10.1109/ISSCC.1996.488546
A. Suzuki, T. Kobayashi, T. Hamano, H. Hatada, A. Kawasumi, F. Matsuoka, K. Ishimaru, M. Takahashi, M. Nishigohri, Y. Okayama, Y. Unno, M. Kakumu, J. Tsujimoto
{"title":"A 400 MHz 4.5 Mb synchronous BiCMOS SRAM with alternating bit-line loads","authors":"A. Suzuki, T. Kobayashi, T. Hamano, H. Hatada, A. Kawasumi, F. Matsuoka, K. Ishimaru, M. Takahashi, M. Nishigohri, Y. Okayama, Y. Unno, M. Kakumu, J. Tsujimoto","doi":"10.1109/ISSCC.1996.488546","DOIUrl":"https://doi.org/10.1109/ISSCC.1996.488546","url":null,"abstract":"This SRAM explores the feasibility of high-capacity, high-speed off-chip cache memories. The SRAM has a 4.5 Mb capacity with a 128 k/spl times/36 b and 256 k/spl times/18 b configuration. It is fabricated in 0.3 /spl mu/m BiCMOS technology. Alternating bit-line loads and skew-compensated write circuitry with a switched delay decoder are used to raise maximum clock frequency.","PeriodicalId":162539,"journal":{"name":"1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115085745","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A 1.8 V, 5.4 mW, digital-audio /spl Sigma//spl Delta/ modulator in 1.2 /spl mu/m CMOS 1.8 V, 5.4 mW，数字音频/spl Sigma//spl Delta/调制器，1.2 /spl mu/m CMOS
1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC Pub Date : 1996-02-08 DOI: 10.1109/ISSCC.1996.488582
S. Rabii, B. Wooley
{"title":"A 1.8 V, 5.4 mW, digital-audio /spl Sigma//spl Delta/ modulator in 1.2 /spl mu/m CMOS","authors":"S. Rabii, B. Wooley","doi":"10.1109/ISSCC.1996.488582","DOIUrl":"https://doi.org/10.1109/ISSCC.1996.488582","url":null,"abstract":"This experimental switched-capacitor /spl Sigma//spl Delta/ modulator achieves 92 dB dynamic range for a signal bandwidth of dc to 25 kHz while operating from 1.8 V supply. The supply voltage is consistent with the end-of-life of two battery cells in series. The fully-differential circuit has been integrated in a 5 V, 1.2 /spl mu/m CMOS technology with poly-n/sup +/ capacitors.","PeriodicalId":162539,"journal":{"name":"1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC","volume":"162 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123031104","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Camera on a chip 芯片摄像头
1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC Pub Date : 1996-02-08 DOI: 10.1109/ISSCC.1996.488499
Alex Dickinson, Bryan D. Ackland
{"title":"Camera on a chip","authors":"Alex Dickinson, Bryan D. Ackland","doi":"10.1109/ISSCC.1996.488499","DOIUrl":"https://doi.org/10.1109/ISSCC.1996.488499","url":null,"abstract":"Recent advances in video compression and digital networking technology, combined with the ever increasing power of PCs and workstations, are creating enormous opportunities to develop new multimedia products and services built upon sophisticated voice, data, image and video processing. This will create a significant demand for compact, low-cost, low-power electronic cameras for video and still image capture. These cameras will be a standard peripheral on all PCs bundled for multimedia applications. Given that in excess of 60M PCs will be sold this year, a sizable new market for electronic cameras is being created.","PeriodicalId":162539,"journal":{"name":"1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127667093","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 91
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