A 7.68 GIPS 3.84 GB/s 1W parallel image processing RAM integrating a 16 Mb DRAM and 128 processors

Abstract

A parallel image processing RAM (PIP-RAM) integrates a 16 Mb DRAM and 128 processor elements (PEs) on a single chip in 64 Mb DRAM process technology. There are three general design requirements when integrating DRAMs and processors onto a single chip: high-data-rate random access, low-power dissipation, and efficiently synchronized DRAM and processor. The PIP-RAM employs three circuit techniques in response to these requirements: (1) a paged-segmentation accessing (PSA), (2) a clocked low-voltage-swing differential-charge-transfer (CLD), and (3) a multiphase synchronization DRAM control (MSD) that uses a multiple-stage PLL. Large memory capacity and high-data-rate random access achieved by these techniques make the PIP-RAM suitable for image processing of large-scale, full-color pictures.