T. Kuroda, Y. Matsuda, K. Ishikawa, K. Tachikawa, M. Masuyama, M. Asaumi, M. Niwayama, T. Yamada, Y. Miyata, N. Niisoe, S. Terakawa
{"title":"A 1/4 inch 330 k square pixel progressive-scan IT-CCD image sensor with submicrometer channel width","authors":"T. Kuroda, Y. Matsuda, K. Ishikawa, K. Tachikawa, M. Masuyama, M. Asaumi, M. Niwayama, T. Yamada, Y. Miyata, N. Niisoe, S. Terakawa","doi":"10.1109/ISSCC.1996.488563","DOIUrl":null,"url":null,"abstract":"A 1/4 inch IT-CCD with 640 (H)/spl times/480 (V) square pixels is described. In a progressive-scan CCD, the gate area for charge storage during vertical charge transfer decreases to less than half compared with a conventional CCD. The first objective is increased charge handling capability per unit gate area to compensate for the gate area decrease. The second is suppression of narrow and/or short-channel effect that is important in IT-CCD with channel area shrinkage. Two techniques overcome these problems. One is to avoid the decrease of effective channel width due to alignment error in stepper lithography that has a significant influence in a narrow-channel CCD. To this end, pixel design and processing are improved so one mask step for the buried channel determines channel width (regulated by three mask steps in a conventional CCD). The other is improvement of the doping profile.","PeriodicalId":162539,"journal":{"name":"1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC","volume":"24 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1996-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.1996.488563","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 6
Abstract
A 1/4 inch IT-CCD with 640 (H)/spl times/480 (V) square pixels is described. In a progressive-scan CCD, the gate area for charge storage during vertical charge transfer decreases to less than half compared with a conventional CCD. The first objective is increased charge handling capability per unit gate area to compensate for the gate area decrease. The second is suppression of narrow and/or short-channel effect that is important in IT-CCD with channel area shrinkage. Two techniques overcome these problems. One is to avoid the decrease of effective channel width due to alignment error in stepper lithography that has a significant influence in a narrow-channel CCD. To this end, pixel design and processing are improved so one mask step for the buried channel determines channel width (regulated by three mask steps in a conventional CCD). The other is improvement of the doping profile.