5.4 GOPS linear array architecture DSP for video-format conversion

1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC Pub Date : 1996-02-08 DOI:10.1109/ISSCC.1996.488594

M. Kurokawa, A. Hashiguchi, K. Nakamura, H. Okuda, K. Aoyama, T. Yamazaki, M. Ohki, M. Soneda, K. Seno, I. Kumata, M. Aikawa, H. Hanaki, S. Iwase

引用次数: 10

Abstract

A programmable DSP with linear-array architecture for real-time video processing, including video format conversion, has 4320 SIMD processor elements, has a peak processing rate of 5.4 GOPS, and can be applied to HDTV signals with its 75 MHz peak I/O clock rate. Sufficient programmability is provided to execute video-format conversion, such as image-size conversion (ISC) and Y/C separation, and picture-quality improvement, such as noise reduction and image enhancement.

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5.4视频格式转换的GOPS线性阵列架构DSP

一种用于实时视频处理(包括视频格式转换)的线性阵列可编程DSP，具有4320个SIMD处理器单元，峰值处理速率为5.4 GOPS，可应用于HDTV信号，峰值I/O时钟速率为75 MHz。提供了足够的可编程性来执行视频格式转换，例如图像大小转换和Y/C分离，以及改善图像质量，例如减少噪声和增强图像。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC

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