A 400 MHz 4.5 Mb synchronous BiCMOS SRAM with alternating bit-line loads

Abstract

This SRAM explores the feasibility of high-capacity, high-speed off-chip cache memories. The SRAM has a 4.5 Mb capacity with a 128 k/spl times/36 b and 256 k/spl times/18 b configuration. It is fabricated in 0.3 /spl mu/m BiCMOS technology. Alternating bit-line loads and skew-compensated write circuitry with a switched delay decoder are used to raise maximum clock frequency.