1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC最新文献

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A 16 cm/sup 2/ monolithic multiprocessor system integrating 9 video signal-processing elements 一个16cm /sup /单片多处理器系统,集成了9个视频信号处理元件
J. Otterstedt, K. Gaedke, M. Kuboschek, H. Schroder, A. Werner
{"title":"A 16 cm/sup 2/ monolithic multiprocessor system integrating 9 video signal-processing elements","authors":"J. Otterstedt, K. Gaedke, M. Kuboschek, H. Schroder, A. Werner","doi":"10.1109/ISSCC.1996.488630","DOIUrl":"https://doi.org/10.1109/ISSCC.1996.488630","url":null,"abstract":"The 16.6 cm/sup 2/ integrated circuit (LAIC) integrates a MIMD based multiprocessor system for real-time video coding applications (H.261, MPEG-1 and MPEG-2) that consists of identical bus-connected processing elements (PEs). Each PE contains a RISC processor core for controlling tasks and a low-level coprocessor (LCP) for fast processing of computation-intensive convolution-type tasks. The LCP consists of an arithmetic processing unit (APU), a controlling unit (CU), and a local memory (LM). The APU consists of four identical parallel and pipelined data paths with a common multi-operand accumulator. The results of the APU are stored in the LM for faster access. Address sequences for the LM are generated by the microprogrammable CU which is supervised by the RISC processor. At a clock rate of 66 MHz, a single PE provides a peak arithmetic performance of more than 1 GOPS. The basic arithmetic units (adders, multipliers, multioperand accu, shifter and ALU) and the single-, dual- and quad-port SRAMs used in RISC and LCP are implemented as full-custom macros.","PeriodicalId":162539,"journal":{"name":"1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132840364","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Single-electron-memory integrated circuit for giga-to-tera bit storage 用于千兆比特存储的单电子存储器集成电路
K. Yano, T. Ishii, T. Sano, T. Mine, F. Murai, K. Seki
{"title":"Single-electron-memory integrated circuit for giga-to-tera bit storage","authors":"K. Yano, T. Ishii, T. Sano, T. Mine, F. Murai, K. Seki","doi":"10.1109/ISSCC.1996.488617","DOIUrl":"https://doi.org/10.1109/ISSCC.1996.488617","url":null,"abstract":"A single-electron-based integrated circuit is presented. An 8/spl times/8 b memory-cell array demonstrates read/write, ushering in a new phase of research on single-electron devices.","PeriodicalId":162539,"journal":{"name":"1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC","volume":"356 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132010746","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 25
A 1 V multi-threshold voltage CMOS DSP with an efficient power management technique for mobile phone application 一种1v多阈值电压CMOS DSP,具有高效的手机电源管理技术
S. Mutoh, S. Shigematsu, Y. Matsuya, H. Fukuda, J. Yamada
{"title":"A 1 V multi-threshold voltage CMOS DSP with an efficient power management technique for mobile phone application","authors":"S. Mutoh, S. Shigematsu, Y. Matsuya, H. Fukuda, J. Yamada","doi":"10.1109/ISSCC.1996.488556","DOIUrl":"https://doi.org/10.1109/ISSCC.1996.488556","url":null,"abstract":"A low-power digital signal processor (DSP) is the key component for battery-driven mobile phone equipment since a vast amount of data needs to be processed for multimedia use. Reduced supply voltage is a direct approach to power reduction. This 1 V DSPLSI with 26 MOPS and 1.1 mW/MOPS performance adopts a multi-threshold-voltage CMOS (MTCMOS) technique. A small embedded power-management processor decreases power during waiting periods.","PeriodicalId":162539,"journal":{"name":"1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132411952","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 74
A 1.5 V 8b 8 mW BiCMOS video A/D converter 一个1.5 V 8b 8mw BiCMOS视频A/D转换器
H. Hasegawa, M. Yotsuyanagi, M. Satoh, M. Ishida, M. Yamaguchi
{"title":"A 1.5 V 8b 8 mW BiCMOS video A/D converter","authors":"H. Hasegawa, M. Yotsuyanagi, M. Satoh, M. Ishida, M. Yamaguchi","doi":"10.1109/ISSCC.1996.488637","DOIUrl":"https://doi.org/10.1109/ISSCC.1996.488637","url":null,"abstract":"Video ADCs embedded in mixed-signal system LSIs for battery-operated, hand-held multimedia terminals must operate at 0.9-1.5 V supply to reduce system power. By combining the high transconductance and good matching of bipolar transistors with the circuit flexibility of MOS switched capacitor (SC) circuits, a 1.5 V BiCMOS video ADC shows analog BiCMOS has potentially higher performance than CMOS even at 1.5 V.","PeriodicalId":162539,"journal":{"name":"1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114937409","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
An 80 MHz 80 mW 8 b CMOS folding A/D converter with distributed T/H preprocessing 采用分布式T/H预处理的80mhz 80mw 8 b CMOS折叠式A/D转换器
A. Venes, R. van de Plassche
{"title":"An 80 MHz 80 mW 8 b CMOS folding A/D converter with distributed T/H preprocessing","authors":"A. Venes, R. van de Plassche","doi":"10.1109/ISSCC.1996.488635","DOIUrl":"https://doi.org/10.1109/ISSCC.1996.488635","url":null,"abstract":"Successful implementation of folding and interpolation techniques in high-speed A/D converters has been demonstrated in both bipolar and, more recently, CMOS technology. The folding architecture can be considered as a time-continuous two-step architecture. This means that a sample-and-hold amplifier is not necessary in this type of A/D converter. However, due to the folding operation, the internal frequency in the analog folding preprocessing will be a multiple of the input signal frequency. The result is a limited analog input signal frequency, less than full flash A/D converters achieve. This paper describes an A/D converter architecture in 0.5 /spl mu/m CMOS technology, incorporating a distributed track-and-hold (T/H) operation in the analog folding preprocessing, overcoming the previously-mentioned limitation, Maximum clock frequency is 80 MHz at a power dissipation of 80 mW from a 3.3 V supply voltage. The analog preprocessing reduces the requirements for the differential T/H amplifiers equal to the number of reference operations compared to a single T/H amplifier in front of the A/D converter.","PeriodicalId":162539,"journal":{"name":"1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116477833","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 29
A CMOS front-end for CCD cameras 用于CCD相机的CMOS前端
C. Mangelsdorf, Katsu Nakamura, S. Ho, Todd L. Brooks, K. Nishio, H. Matsumoto
{"title":"A CMOS front-end for CCD cameras","authors":"C. Mangelsdorf, Katsu Nakamura, S. Ho, Todd L. Brooks, K. Nishio, H. Matsumoto","doi":"10.1109/ISSCC.1996.488564","DOIUrl":"https://doi.org/10.1109/ISSCC.1996.488564","url":null,"abstract":"Most modern camcorders use digital processing exclusively in the signal path for better performance even though image information from the CCD and the signal recorded on the internal VTR are both in analog form. Before the signal can be digitized, however, extensive clamping and low-noise gain must be applied. Consumer pressure for small camcorder size and low power have lead to the development of a system in which all the functions previously residing on a bipolar chip have been incorporated on the same CMOS die with the ADC, including a CDS block, an amplifier with variable gain from 0 to 34 dB, a black-level correction loop, an input clamp and a voltage reference. An emitter follower buffer is traditionally used between the CCD and the rest of the system for line driving, but this is the only portion of the analog signal chain external to the chip.","PeriodicalId":162539,"journal":{"name":"1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132778539","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
A 64-entry 167 MHz fully-associative TLB for a RISC microprocessor 用于RISC微处理器的64入口167 MHz全关联TLB
E. Anderson
{"title":"A 64-entry 167 MHz fully-associative TLB for a RISC microprocessor","authors":"E. Anderson","doi":"10.1109/ISSCC.1996.488717","DOIUrl":"https://doi.org/10.1109/ISSCC.1996.488717","url":null,"abstract":"Memory subsystems of RISC microprocessors require efficient translation of virtual addresses to physical addresses. A fully-associative embedded translation lookaside buffer (TLB) provides this function in a microprocessor. Two identical TLBs are used: one for instructions and another for data. The CPU architecture requires that the TLB translate a new address every cycle.","PeriodicalId":162539,"journal":{"name":"1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122376862","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A 1.4 Gb/s 12-channel parallel laser diode driver IC for optical interconnections 用于光互连的1.4 Gb/s 12通道并行激光二极管驱动IC
T. Umeda, K. Yoshihara, M. Konno, K. Kaminishi, K. Hirakawa
{"title":"A 1.4 Gb/s 12-channel parallel laser diode driver IC for optical interconnections","authors":"T. Umeda, K. Yoshihara, M. Konno, K. Kaminishi, K. Hirakawa","doi":"10.1109/ISSCC.1996.488624","DOIUrl":"https://doi.org/10.1109/ISSCC.1996.488624","url":null,"abstract":"The authors present a 12-channel parallel laser diode (LD) driver with 16.8 Gb/s throughput. The driver IC creates skew-free output and provides temperature compensation of the optical power of the LD. The IC also suppresses ringing oscillation and crosstalk. The die is 2.5x3.5 mm/sup 2/ using a 15 GHz f/sub /spl tau// Si bipolar process. The power supply voltage is 5 V and the power consumption is 4.2 W including the PECL level input signal consumption of 1.1 W and the output signal consumption of 2.0 W at 3l mApp + 2 mA bias.","PeriodicalId":162539,"journal":{"name":"1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130259830","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A 900 MHz frequency synthesizer with integrated LC voltage-controlled oscillator 900mhz频率合成器,集成LC压控振荡器
A. Ali, Joo Leong Tham
{"title":"A 900 MHz frequency synthesizer with integrated LC voltage-controlled oscillator","authors":"A. Ali, Joo Leong Tham","doi":"10.1109/ISSCC.1996.488730","DOIUrl":"https://doi.org/10.1109/ISSCC.1996.488730","url":null,"abstract":"Integration of general-purpose frequency synthesizers usually requires a BiCMOS process and necessitates a compromise between the level of integration and performance. Frequency synthesizers with extensive channel programming flexibility and low phase noise typically require external voltage-controlled oscillators (VCOs) while highly-integrated synthesizers utilizing on-chip VCOs tend to exhibit degraded phase-noise performance. The frequency synthesizer presented here features low reference spurs and low phase-noise and is fully-integrated with the exception of an external crystal and an RC loop-filter. It uses a 25 GHz f/sub /spl tau// silicon bipolar process and is for 900 MHz ISM band applications and operates over a supply voltage range of 2.7 V to 5.0 V. The integration level is achieved by a simplified pulse-swallow architecture that provides 41 channels with a 600 kHz spacing and requires a 6 bit programming word.","PeriodicalId":162539,"journal":{"name":"1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129875763","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 33
A 98 mm/sup 2/ 3.3 V 64 Mb flash memory with FN-NOR type 4-level cell 一个98毫米/sup 2/ 3.3 V 64 Mb闪存,带有FN-NOR型4级电池
M. Ohkawa, H. Sugawara, N. Sudo, M. Tsukiji, K. Nakagawa, M. Kawata, K. Oyama, T. Takeshima, S. Ohya
{"title":"A 98 mm/sup 2/ 3.3 V 64 Mb flash memory with FN-NOR type 4-level cell","authors":"M. Ohkawa, H. Sugawara, N. Sudo, M. Tsukiji, K. Nakagawa, M. Kawata, K. Oyama, T. Takeshima, S. Ohya","doi":"10.1109/ISSCC.1996.488503","DOIUrl":"https://doi.org/10.1109/ISSCC.1996.488503","url":null,"abstract":"A 64 Mb flash memory has a multi-level cell and 64-memory-cell parallel programming. 98 mm/sup 2/ die uses 0.4 /spl mu/m CMOS and 4-levels (2b) per cell. 3.3 V operation and 6.3 /spl mu/s/B programming are achieved by using a Fowler-Nordheim (FN) NOR memory cell. Drain-voltage controlled multilevel programming (DCMP) is the key technology for simultaneous multi-level programming in the chip. To implement DCMP, a parallel multi-level verify (PMV) circuit and the compact multi-level sense amplifier (CMS), which enable a 64-memory-cells parallel programming operation (program/program verify), are used.","PeriodicalId":162539,"journal":{"name":"1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121424260","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
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