1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC最新文献_第5页

A 16 cm/sup 2/ monolithic multiprocessor system integrating 9 video signal-processing elements 一个16cm /sup /单片多处理器系统，集成了9个视频信号处理元件

1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC Pub Date : 1996-02-08 DOI: 10.1109/ISSCC.1996.488630

J. Otterstedt, K. Gaedke, M. Kuboschek, H. Schroder, A. Werner

{"title":"A 16 cm/sup 2/ monolithic multiprocessor system integrating 9 video signal-processing elements","authors":"J. Otterstedt, K. Gaedke, M. Kuboschek, H. Schroder, A. Werner","doi":"10.1109/ISSCC.1996.488630","DOIUrl":"https://doi.org/10.1109/ISSCC.1996.488630","url":null,"abstract":"The 16.6 cm/sup 2/ integrated circuit (LAIC) integrates a MIMD based multiprocessor system for real-time video coding applications (H.261, MPEG-1 and MPEG-2) that consists of identical bus-connected processing elements (PEs). Each PE contains a RISC processor core for controlling tasks and a low-level coprocessor (LCP) for fast processing of computation-intensive convolution-type tasks. The LCP consists of an arithmetic processing unit (APU), a controlling unit (CU), and a local memory (LM). The APU consists of four identical parallel and pipelined data paths with a common multi-operand accumulator. The results of the APU are stored in the LM for faster access. Address sequences for the LM are generated by the microprogrammable CU which is supervised by the RISC processor. At a clock rate of 66 MHz, a single PE provides a peak arithmetic performance of more than 1 GOPS. The basic arithmetic units (adders, multipliers, multioperand accu, shifter and ALU) and the single-, dual- and quad-port SRAMs used in RISC and LCP are implemented as full-custom macros.","PeriodicalId":162539,"journal":{"name":"1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132840364","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 13

Single-electron-memory integrated circuit for giga-to-tera bit storage 用于千兆比特存储的单电子存储器集成电路

1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC Pub Date : 1996-02-08 DOI: 10.1109/ISSCC.1996.488617

K. Yano, T. Ishii, T. Sano, T. Mine, F. Murai, K. Seki

引用次数: 25

A 1 V multi-threshold voltage CMOS DSP with an efficient power management technique for mobile phone application 一种1v多阈值电压CMOS DSP，具有高效的手机电源管理技术

1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC Pub Date : 1996-02-08 DOI: 10.1109/ISSCC.1996.488556

S. Mutoh, S. Shigematsu, Y. Matsuya, H. Fukuda, J. Yamada

引用次数: 74

A 1.5 V 8b 8 mW BiCMOS video A/D converter 一个1.5 V 8b 8mw BiCMOS视频A/D转换器

1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC Pub Date : 1996-02-08 DOI: 10.1109/ISSCC.1996.488637

H. Hasegawa, M. Yotsuyanagi, M. Satoh, M. Ishida, M. Yamaguchi

引用次数: 3

An 80 MHz 80 mW 8 b CMOS folding A/D converter with distributed T/H preprocessing 采用分布式T/H预处理的80mhz 80mw 8 b CMOS折叠式A/D转换器

1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC Pub Date : 1996-02-08 DOI: 10.1109/ISSCC.1996.488635

A. Venes, R. van de Plassche

{"title":"An 80 MHz 80 mW 8 b CMOS folding A/D converter with distributed T/H preprocessing","authors":"A. Venes, R. van de Plassche","doi":"10.1109/ISSCC.1996.488635","DOIUrl":"https://doi.org/10.1109/ISSCC.1996.488635","url":null,"abstract":"Successful implementation of folding and interpolation techniques in high-speed A/D converters has been demonstrated in both bipolar and, more recently, CMOS technology. The folding architecture can be considered as a time-continuous two-step architecture. This means that a sample-and-hold amplifier is not necessary in this type of A/D converter. However, due to the folding operation, the internal frequency in the analog folding preprocessing will be a multiple of the input signal frequency. The result is a limited analog input signal frequency, less than full flash A/D converters achieve. This paper describes an A/D converter architecture in 0.5 /spl mu/m CMOS technology, incorporating a distributed track-and-hold (T/H) operation in the analog folding preprocessing, overcoming the previously-mentioned limitation, Maximum clock frequency is 80 MHz at a power dissipation of 80 mW from a 3.3 V supply voltage. The analog preprocessing reduces the requirements for the differential T/H amplifiers equal to the number of reference operations compared to a single T/H amplifier in front of the A/D converter.","PeriodicalId":162539,"journal":{"name":"1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116477833","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 29

A CMOS front-end for CCD cameras 用于CCD相机的CMOS前端

1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC Pub Date : 1996-02-08 DOI: 10.1109/ISSCC.1996.488564

C. Mangelsdorf, Katsu Nakamura, S. Ho, Todd L. Brooks, K. Nishio, H. Matsumoto

引用次数: 14

A 64-entry 167 MHz fully-associative TLB for a RISC microprocessor 用于RISC微处理器的64入口167 MHz全关联TLB

1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC Pub Date : 1996-02-08 DOI: 10.1109/ISSCC.1996.488717

E. Anderson

引用次数: 3

A 1.4 Gb/s 12-channel parallel laser diode driver IC for optical interconnections 用于光互连的1.4 Gb/s 12通道并行激光二极管驱动IC

1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC Pub Date : 1996-02-08 DOI: 10.1109/ISSCC.1996.488624

T. Umeda, K. Yoshihara, M. Konno, K. Kaminishi, K. Hirakawa

引用次数: 5

A 900 MHz frequency synthesizer with integrated LC voltage-controlled oscillator 900mhz频率合成器，集成LC压控振荡器

1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC Pub Date : 1996-02-08 DOI: 10.1109/ISSCC.1996.488730

A. Ali, Joo Leong Tham

引用次数: 33

A 98 mm/sup 2/ 3.3 V 64 Mb flash memory with FN-NOR type 4-level cell 一个98毫米/sup 2/ 3.3 V 64 Mb闪存，带有FN-NOR型4级电池

1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC Pub Date : 1996-02-08 DOI: 10.1109/ISSCC.1996.488503

M. Ohkawa, H. Sugawara, N. Sudo, M. Tsukiji, K. Nakagawa, M. Kawata, K. Oyama, T. Takeshima, S. Ohya

引用次数: 11