An 80 MHz 80 mW 8 b CMOS folding A/D converter with distributed T/H preprocessing

Abstract

Successful implementation of folding and interpolation techniques in high-speed A/D converters has been demonstrated in both bipolar and, more recently, CMOS technology. The folding architecture can be considered as a time-continuous two-step architecture. This means that a sample-and-hold amplifier is not necessary in this type of A/D converter. However, due to the folding operation, the internal frequency in the analog folding preprocessing will be a multiple of the input signal frequency. The result is a limited analog input signal frequency, less than full flash A/D converters achieve. This paper describes an A/D converter architecture in 0.5 /spl mu/m CMOS technology, incorporating a distributed track-and-hold (T/H) operation in the analog folding preprocessing, overcoming the previously-mentioned limitation, Maximum clock frequency is 80 MHz at a power dissipation of 80 mW from a 3.3 V supply voltage. The analog preprocessing reduces the requirements for the differential T/H amplifiers equal to the number of reference operations compared to a single T/H amplifier in front of the A/D converter.