用于RISC微处理器的64入口167 MHz全关联TLB

1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC Pub Date : 1996-02-08 DOI:10.1109/ISSCC.1996.488717

E. Anderson

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引用次数: 3

摘要

RISC微处理器的内存子系统需要有效地将虚拟地址转换为物理地址。在微处理器中，一个完全关联的嵌入式翻译暂存缓冲区(TLB)提供了这个功能。使用两个相同的tlb:一个用于指令，另一个用于数据。CPU架构要求TLB每个周期转换一个新地址。

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A 64-entry 167 MHz fully-associative TLB for a RISC microprocessor

Memory subsystems of RISC microprocessors require efficient translation of virtual addresses to physical addresses. A fully-associative embedded translation lookaside buffer (TLB) provides this function in a microprocessor. Two identical TLBs are used: one for instructions and another for data. The CPU architecture requires that the TLB translate a new address every cycle.

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1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC

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