发布求助
文献互助 智能选刊 最新文献

1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC最新文献

筛选
英文 中文
A 0.8 /spl mu/m CMOS 2.5 Gb/s oversampled receiver for serial links 一个0.8 /spl mu/m CMOS 2.5 Gb/s过采样串行链路接收器
1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC Pub Date : 1996-02-08 DOI: 10.1109/ISSCC.1996.488570
Chih-Kong Ken Yang, M. Horowitz
{"title":"A 0.8 /spl mu/m CMOS 2.5 Gb/s oversampled receiver for serial links","authors":"Chih-Kong Ken Yang, M. Horowitz","doi":"10.1109/ISSCC.1996.488570","DOIUrl":"https://doi.org/10.1109/ISSCC.1996.488570","url":null,"abstract":"The demand for higher bit rates by the communications industry has led to the development of high bit rate and low cost serial link interface chips. Recently, interest has grown in using modest CMOS technology to achieve similar bit rates. This work achieves SONET OC-48 (2.488 Gbps) rates with 0.8 /spl mu/m CMOS technology. Because the data rate is near the process unity-gain frequency, a parallel architecture is used to demultiplex the data stream at the input. N precisely-spaced clocks that run at 1/N of the data rate are used. Instead of a conventional analog PLL that would require low noise sensitivity, this work explores oversampling each data bit and using digital logic to select the proper bit values. Although data is not sampled at the center of the eye, the digital loop can choose the best sample with bandwidth roughly the data transition rate.","PeriodicalId":162539,"journal":{"name":"1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133507325","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A 1.5 V 900 MHz downconversion mixer 1.5 V 900 MHz下变频混频器
1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC Pub Date : 1996-02-08 DOI: 10.1109/ISSCC.1996.488508
OOMHz Downconversion Mixer
{"title":"A 1.5 V 900 MHz downconversion mixer","authors":"OOMHz Downconversion Mixer","doi":"10.1109/ISSCC.1996.488508","DOIUrl":"https://doi.org/10.1109/ISSCC.1996.488508","url":null,"abstract":"The demand for fewer batteries and lighter weight in portable RF transceivers has motivated efforts to reduce the supply voltage of both analog and digital building blocks of such systems. In front-end RF circuits, however, trade-offs among six parameters have constantly challenged the designers: noise, power dissipation, linearity, voltage headroom, gain, and operating frequency. While upconversion mixers with supplies as low as 2 V have been reported, noise, speed, and supply rejection issues prohibit the use of such topologies for downconversion. This 900 MHz downconversion mixer employs circuit techniques to relax some of the above trade-offs. The fully-differential circuit consists of a core and an output buffer/amplifier, and operates from a 1.5 V supply.","PeriodicalId":162539,"journal":{"name":"1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC","volume":"103 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122439674","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 22
Implementing application specific memory 实现特定于应用程序的内存
1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC Pub Date : 1996-02-08 DOI: 10.1109/ISSCC.1996.488614
R. Foss
{"title":"Implementing application specific memory","authors":"R. Foss","doi":"10.1109/ISSCC.1996.488614","DOIUrl":"https://doi.org/10.1109/ISSCC.1996.488614","url":null,"abstract":"Successful realization of application specific memory devices (ASM) requires designing onto existing standard ASIC or memory processes, at least in the short term, to avoid the cost and time penalties of developing new processes. Existing memory and ASIC processes have been optimized independently so there are well-recognized problems in seeking to combine memory and logic on a single chip. A number of applications demanding such a combination are emerging that warrant the design effort to overcome such problems. While processes better-suited to mixed memory and logic will become more generally available, the designer of an ASM today generally must find a way to add higher-density memory onto an ASIC chip, or, if a still greater capacity is needed, add efficient logic to a DRAM process. Neither task is as easy as it may seem.","PeriodicalId":162539,"journal":{"name":"1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC","volume":"212 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121227360","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
A 500 MHz 288 kb CMOS SRAM macro for on-chip cache 用于片上缓存的500 MHz 288 kb CMOS SRAM宏
1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC Pub Date : 1996-02-08 DOI: 10.1109/ISSCC.1996.488551
K. Furumochi, H. Shimizu, M. Fujita, T. Akita, T. Izawa, M. Katsube, K. Aoyama, S. Kawamura
{"title":"A 500 MHz 288 kb CMOS SRAM macro for on-chip cache","authors":"K. Furumochi, H. Shimizu, M. Fujita, T. Akita, T. Izawa, M. Katsube, K. Aoyama, S. Kawamura","doi":"10.1109/ISSCC.1996.488551","DOIUrl":"https://doi.org/10.1109/ISSCC.1996.488551","url":null,"abstract":"A 288 kb (4 kw by 72 b) embedded SRAM macro operates at 500 MHz. A modular design using a double-stage clock generator achieves the word-bit size flexibility required for embedded SRAM. This macro is intended to be used as an on-chip cache for high-speed CPUs.","PeriodicalId":162539,"journal":{"name":"1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC","volume":"252 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121249424","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
One-chip TV 单晶片的电视
1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC Pub Date : 1996-02-08 DOI: 10.1109/ISSCC.1996.488500
L. Nederlof
{"title":"One-chip TV","authors":"L. Nederlof","doi":"10.1109/ISSCC.1996.488500","DOIUrl":"https://doi.org/10.1109/ISSCC.1996.488500","url":null,"abstract":"One-chip TV is a system that can do all the signal processing between the tuner output and the inputs of the power amplifiers of the display and sound systems. It is a very application specific system on silicon, targeted at the standard definition TV receiver market (NTSC, PAL and SECAM). In the world of \"Systems on Silicon\" it is a rather unique system, since all signal processing is analog, while the control and adjustment signals are digital. As a product, it can be applied anywhere a standard TV receiving function is needed: TV sets, TV receiver plug-in cards for PCs, and so on. The current system is the result of a number of cooperating influences: market characteristics and set maker requirements, current TV standards, and capabilities of current silicon technology. In this paper these influences are explored and it is shown how they have shaped the present form of one-chip TV.","PeriodicalId":162539,"journal":{"name":"1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114637015","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Elastic-Vt CMOS circuits for multiple on-chip power control 弹性vt CMOS电路用于多个片上电源控制
1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC Pub Date : 1996-02-08 DOI: 10.1109/ISSCC.1996.488627
M. Mizuno, K. Furuta, S. Narita, H. Abiko, I. Sakai, M. Yamashina
{"title":"Elastic-Vt CMOS circuits for multiple on-chip power control","authors":"M. Mizuno, K. Furuta, S. Narita, H. Abiko, I. Sakai, M. Yamashina","doi":"10.1109/ISSCC.1996.488627","DOIUrl":"https://doi.org/10.1109/ISSCC.1996.488627","url":null,"abstract":"The elastic-Vt CMOS (EVTCMOS) circuit design controls MOS transistor source (not substrate) voltages, so fabrication requires no special steps. The post-fabrication threshold voltages can be switched back and forth between high Vt (sleep mode) and low Vt (active mode), and can be also controlled as a means of reducing the sensitivity to device-parameter deviations and operating-environment variations. This results in reduction of switching time between sleep and active modes, and in reduced static power consumption in sleep mode.","PeriodicalId":162539,"journal":{"name":"1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121555235","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
A 2 ns zero wait state, 32 kB semi-associative L1 cache 2秒零等待状态，32 kB半关联L1缓存
1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC Pub Date : 1996-02-08 DOI: 10.1109/ISSCC.1996.488550
J. Covino, J. Connor, D. Evans, A. Roberts, Marcel Robillard, Jose Sousa, Luigi Ternullo
{"title":"A 2 ns zero wait state, 32 kB semi-associative L1 cache","authors":"J. Covino, J. Connor, D. Evans, A. Roberts, Marcel Robillard, Jose Sousa, Luigi Ternullo","doi":"10.1109/ISSCC.1996.488550","DOIUrl":"https://doi.org/10.1109/ISSCC.1996.488550","url":null,"abstract":"A 32 kB, semi-associative bit dimension, L1 cache test site uses 0.5 /spl mu/m 2.5 V CMOS. The technology features an Leff of 0.25 /spl mu/m, a 7 nm Tox, shallow trench isolation, and a tungsten local interconnect. Four of the available five levels of metal are used. The cache consists of a data-storage array (DSA) macro, a content-addressable memory (CAM) macro, directory macro, and a memory built-in self-test (MBIST) state machine. Measured clock-to-DSA data-out access is 2 ns on nominal hardware. Access includes late-select generation from the CAM. The hardware cycles at access.","PeriodicalId":162539,"journal":{"name":"1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115021347","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A 3.3 V-only 16 Mb flash memory with row-decoding scheme 3.3 v - 16mb带行解码方案的闪存
1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC Pub Date : 1996-02-08 DOI: 10.1109/ISSCC.1996.488506
S. Atsumi, A. Umezawa, M. Kuriyama, H. Banba, N. Ohtsuka, N. Tomita, Y. Iyama, T. Miyaba, R. Sudoh, E. Kamiya, M. Tanimoto, Y. Hiura, Y. Araki, E. Sakagami, N. Arai, S. Mori
{"title":"A 3.3 V-only 16 Mb flash memory with row-decoding scheme","authors":"S. Atsumi, A. Umezawa, M. Kuriyama, H. Banba, N. Ohtsuka, N. Tomita, Y. Iyama, T. Miyaba, R. Sudoh, E. Kamiya, M. Tanimoto, Y. Hiura, Y. Araki, E. Sakagami, N. Arai, S. Mori","doi":"10.1109/ISSCC.1996.488506","DOIUrl":"https://doi.org/10.1109/ISSCC.1996.488506","url":null,"abstract":"A 3.3 V only 16 M flash memory with a row decoding scheme is fabricated in 0.4 /spl mu/m double-well double-metal CMOS. Negative-gate-biased erase enables 3.3 V-only operation, and a double-word-line structure with second aluminum minimizes word-line delay. Row redundancy with self-convergence improves yield. Quasi-differential sensing with address transition detection gives fast random access.","PeriodicalId":162539,"journal":{"name":"1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC","volume":"297 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132443038","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
A 200M sample/s 6b flash ADC in 0.6 /spl mu/m CMOS 一个200米采样/秒6b闪存ADC在0.6 /spl μ m CMOS
1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC Pub Date : 1996-02-08 DOI: 10.1109/ISSCC.1996.488636
J. Spalding, D. Dalton
{"title":"A 200M sample/s 6b flash ADC in 0.6 /spl mu/m CMOS","authors":"J. Spalding, D. Dalton","doi":"10.1109/ISSCC.1996.488636","DOIUrl":"https://doi.org/10.1109/ISSCC.1996.488636","url":null,"abstract":"This 6b flash analog-to-digital converter (ADC) performs the sampling function in a partial-response, maximum-likelihood disk drive read channel. The read channel must process signals with spectral content extending up to half the sampling rate. This requires an ADC with better than 5 effective bits at Nyquist, accomplished here using a full-flash architecture capable of sampling at 200 MHz. To meet cost objectives, the read channel is on 0.6 /spl mu/m single-poly CMOS, where the ADC achieves performance previously seen only on bipolar or BiCMOS processes.","PeriodicalId":162539,"journal":{"name":"1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130691457","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
2D magnetic microsensor with on-chip signal processing for contactless angle measurement 带有片上信号处理的二维磁微传感器，用于非接触角度测量
1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC Pub Date : 1996-02-08 DOI: 10.1109/ISSCC.1996.488641
A. Haberli, M. Schneider, P. Malcovati, R. Castagnetti, F. Maloberti, H. Baltes
{"title":"2D magnetic microsensor with on-chip signal processing for contactless angle measurement","authors":"A. Haberli, M. Schneider, P. Malcovati, R. Castagnetti, F. Maloberti, H. Baltes","doi":"10.1109/ISSCC.1996.488641","DOIUrl":"https://doi.org/10.1109/ISSCC.1996.488641","url":null,"abstract":"This microsystem is the key element for accurate contactless angle measurements in combination with a permanent magnet. The system is based on a novel approach for signal processing using an on-board incremental ADC and a two-dimensional (2D) magnetic microsensor allowing 1/spl deg/ resolution. The system can be used for various wear-free angular positioning control systems in industrial and automotive applications.","PeriodicalId":162539,"journal":{"name":"1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130814179","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 26
首页 上一页 下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：604180095
Book学术官方微信