S. Wong, H. Bhimnathwala, S. Luo, B. Halali, S. Navid
{"title":"A 1 W 830 MHz monolithic BiCMOS power amplifier","authors":"S. Wong, H. Bhimnathwala, S. Luo, B. Halali, S. Navid","doi":"10.1109/ISSCC.1996.488510","DOIUrl":"https://doi.org/10.1109/ISSCC.1996.488510","url":null,"abstract":"A silicon MMIC power amplifier delivers over 1 W of output power at 830 MHz. When biased in class AB, this amplifier provides a 30 dB power gain, a 30% power-add-efficiency (PAE), and 50 dB dynamic gain-control range. This amplifier uses on-chip spiral inductors to provide interstage impedance matching, and incorporates negative impedance cancellation in one stage to boost gain and impedance level. Temperature-compensated biasing provides accurate control of the quiescent current in each amplifier stage.","PeriodicalId":162539,"journal":{"name":"1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC","volume":" 29","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114060581","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A 10 b 120 MSamples/s multiple sampling, single conversion CMOS A/D converter for I/Q demodulator","authors":"J. Eklund, R. Arvidsson","doi":"10.1109/ISSCC.1996.488625","DOIUrl":"https://doi.org/10.1109/ISSCC.1996.488625","url":null,"abstract":"We present a filter that estimates the signals at time Tm=T(n+1/2), where T=1/fs. Then two filters are needed, one I- and one Q-filter. There exists a class of transversal filters that can be implemented in the sampling unit as an analog filter. The filtering is done in the sampling operation, and by decimating the signal to the base band the A/D conversion can be done at low speed. We have investigated the quality of an implementation in a double-metal single-poly 0.8 /spl mu/m CMOS-process.","PeriodicalId":162539,"journal":{"name":"1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC","volume":"40 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114124245","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Digital-phase aligner macro for clock tree compensation with 70 ps jitter","authors":"D. Woeste, M. Dina, T. Nguyen, J. Strom","doi":"10.1109/ISSCC.1996.488542","DOIUrl":"https://doi.org/10.1109/ISSCC.1996.488542","url":null,"abstract":"This paper describes a digital phase aligner (DPA) that can be used to decrease the chip-to-chip clock skew caused by process and temperature variations of the on-chip clock trees in a multiple-chip synchronous system with multiple clock domains. This method adjusts the delay of a variable-delay line to align an output of the clock tree to the clock input of a chip. Delay is added to make the clock tree latency an integral number of cycles. The goal was to design a delay-locked loop over a 8-25 ns cycle time with low jitter, allow multiple uses per ASIC, have the ability to start and stop the external clock without a long period of initialization and be fully testable by level-sensitive scan design (LSSD).","PeriodicalId":162539,"journal":{"name":"1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117300658","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A 900 MHz integrated discrete-time filtering RF front-end","authors":"D. Shen, Chien-Meen Hwang, B. Lusignan, B. Wooley","doi":"10.1109/ISSCC.1996.488511","DOIUrl":"https://doi.org/10.1109/ISSCC.1996.488511","url":null,"abstract":"The authors introduce a radio receiver architecture that avoids external intermediate frequency (IF) filters, while maintaining the selectivity required for narrowband frequency-multiplexed channels. The receiver is based on a subsampling architecture and operates in the 800-900 MHz range. It is a potential candidate for use in applications such as portable mobile data systems, personal communications devices, and cordless telephony. This receiver differs from a superheterodyne architecture in that the mixer is replaced by a sampling circuit and the intermediate frequency filters are replaced by a cascade of downsampling stages employing discrete-time filtering. The process of subsampling, sampling the input signal at a rate lower than the highest frequency components of the input signal, performs a function equivalent to mixing. Because the input is bandlimited by an analog RF filter, the Nyquist criterion is satisfied as long as the sampling rate is more than twice the bandwidth of this filter. The noise filter following the low noise amplifier (LNA) limits the noise bandwidth to prevent wideband noise from aliasing into the signal band and increasing the noise floor.","PeriodicalId":162539,"journal":{"name":"1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124816719","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Bigongiari, S. Brigati, G. Caiulo, G. Franchi, F. Maloberti
{"title":"An 8-Channel 250 MHz BiCMOS discriminator for medical imaging","authors":"A. Bigongiari, S. Brigati, G. Caiulo, G. Franchi, F. Maloberti","doi":"10.1109/ISSCC.1996.488638","DOIUrl":"https://doi.org/10.1109/ISSCC.1996.488638","url":null,"abstract":"Several clinical and diagnostic applications, such as X-ray imaging, digital mammography and nuclear medicine, use imaging techniques employing detectors typical of high-energy physics. The discriminator is a fundamental block in the digital image processing chain since it discriminates useful signals from the background noise and converts them into standardized logic pulses of predefined amplitude and duration for successive digital processing. This paper describes a discriminator IC that operates at up to 250 MHz. The device, realized in a 1.2 /spl mu/m BiCMOS technology, incorporates 8 equal and independent channels and consumes 68 mW per channel. Each channel is composed of a comparator followed by a pulse shaper. The circuit may be interfaced with most detectors as well as digital processors.","PeriodicalId":162539,"journal":{"name":"1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC","volume":"383 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122870679","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A band pass /spl Sigma//spl Delta/ modulator for ultrasound imaging at 160 MHz clock rate","authors":"O. Norman","doi":"10.1109/ISSCC.1996.488586","DOIUrl":"https://doi.org/10.1109/ISSCC.1996.488586","url":null,"abstract":"Phased-array ultrasound imaging is a promising application for /spl Sigma//spl Delta/ converters, where overall analog hardware can be simplified in exchange for increased digital signal processing (DSP) complexity. A 4th-order band-pass modulator for this application in 0.8 /spl mu/m BiCMOS has a 2.5 MHz-wide signal band centered at 5 MHz. To meet system-level specifications, the modulators dynamic range is 84 dB, achieved by sampling at 160 MHz and performing 24 dB of time-gain-control in the modulator. Noise shaping is programmable between band-reject and notch functions for B-mode (wide band) and CW-mode (narrow band) scanning, respectively.","PeriodicalId":162539,"journal":{"name":"1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131314863","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
D. Rossi, M. Pozzoni, G. Ricotti, E. Ravanelli, E. Strizhak, M. Kackprowicz
{"title":"Single-chip smart power camera controller with photodiode current measurement down to 3 nA","authors":"D. Rossi, M. Pozzoni, G. Ricotti, E. Ravanelli, E. Strizhak, M. Kackprowicz","doi":"10.1109/ISSCC.1996.488643","DOIUrl":"https://doi.org/10.1109/ISSCC.1996.488643","url":null,"abstract":"This IC, together with an external 8 b microcontroller, implements all signal conditioning, measuring and power actuation functions required by a photographic camera. All IC functions are programmed by an external microcontroller through a 16 b SPI interface. The internal low-drop regulator (0.1 V drop, 30 mA) supplies both the internal circuitry and the external microcontroller. A bandgap voltage reference is used for low sensitivity to temperature variation. To preserve battery life, the micro can shut down itself and the system by writing a bit that switches off the regulator and brings system current consumption under 500 nA.","PeriodicalId":162539,"journal":{"name":"1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114927479","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
R. Bayruns, O. Lopez, S. Sweeney, Kuohsiung Li, N. Ditrick
{"title":"A wide dynamic range GaAs broadcast satellite tuner IC","authors":"R. Bayruns, O. Lopez, S. Sweeney, Kuohsiung Li, N. Ditrick","doi":"10.1109/ISSCC.1996.488622","DOIUrl":"https://doi.org/10.1109/ISSCC.1996.488622","url":null,"abstract":"Broadcast satellite tuners (BS tuners) used in set top boxes are fed a 950-2150 MHz input from the satellite dish IF. In apartment complexes the IF signal can be split, amplified, and supplied to many units. This IF input spectrum can consist of as many as 50 channels, each ranging in levels from -75 dBm to -15 dBm. Consequently the linearity requirements of the BS tuner are stringent. Typically pin diode attenuators are used at the input of the BS tuner to absorb this dynamic range. A transistor, the bootstrapped gate FET (BGFET), is small and behaves as a low-distortion variable resistor. Using this linear transistor, a BS tuner IC has an IIP3>+10 dBm and an AGC range of 20 dB. The noise figure over the full RF band of 950-2150 MHz is less than 7 dB. The circuit contains an LNA, AG, mixer, and oscillator and draws 50 mA from a +5 V supply. The chip is 0.37 mm/sup 2/ in a low-power GaAs MESFET technology and is packaged in an SOIC-16 package. The circuit is 4 times smaller than a previous GaAs BS tuner.","PeriodicalId":162539,"journal":{"name":"1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116897386","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A 900 MHz CMOS LC-oscillator with quadrature outputs","authors":"A. Rofougaran, J. Rael, M. Rofougaran, A. Abidi","doi":"10.1109/ISSCC.1996.488731","DOIUrl":"https://doi.org/10.1109/ISSCC.1996.488731","url":null,"abstract":"The local oscillator (LO) in a wireless transceiver satisfies many exacting requirements. A variable frequency enables a phase-locked loop (PLL) to servo the LO to a stable lower frequency reference, or to correct frequency errors from measurements on the received signal. A low phase noise ensures little interference with nearby channels. A large LO voltage-swing means that it can drive a mixer with greater linearity. Finally, in single-sideband applications, the LO must supply precise quadrature phases. Low phase noise mandates use of a high-Q resonator to tune the LO, although most RF resonators are usually not integrable on ICs. Quadrature outputs are usually derived from RC phase-shift of a single-phase LO output, but this is susceptible to component inaccuracy and loss in LO amplitude. The authors present a 900 MHz oscillator circuit implemented in 1 /spl mu/m CMOS that affords modestly low-phase noise, has variable frequency with large output swing, and provides quadrature-phase outputs from two identical coupled oscillators, connected in such a way that they exert a mutual squelch when their relative phase is not in quadrature. The coupled oscillators synchronize to exactly the same frequency, in spite of mismatches in their resonant circuits.","PeriodicalId":162539,"journal":{"name":"1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131027546","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Gigabit complementary HFET communication circuits: 16:1 multiplexer, 1:16 demultiplexer and 16/spl times/16 crosspoint switch","authors":"G. la Rue, T.A. Dao","doi":"10.1109/ISSCC.1996.488537","DOIUrl":"https://doi.org/10.1109/ISSCC.1996.488537","url":null,"abstract":"Three high-speed, low-power integrated circuits are intended for data communication applications in space. A 16:1 multiplexer (1.8 Gb/s, 53 mW), 1:16 demultiplexer (1.1 Gbps/96 mW) and 16/spl times/16 crosspoint switch (1.0 Gb/s, 510 mW) circuits are fabricated using a 0.7 /spl mu/m complementary heterojunction field effect transistor (CHFET) process with cut-off frequencies of about 30 GHz for n-channel and about 6 GHz for p-channel transistors.","PeriodicalId":162539,"journal":{"name":"1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132873726","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}