1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC最新文献_第2页

Circuit and system challenges in IR wireless communication 红外无线通信中的电路和系统挑战

1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC Pub Date : 1996-02-08 DOI: 10.1109/ISSCC.1996.488733

M. Ritter, F. Gfeller, W. Hirt, D. Rogers, S. Gowda

引用次数: 12

A 300 MHz, 3.3 V 1 Mb SRAM fabricated in a 0.5 /spl mu/m CMOS process 以0.5 /spl mu/m CMOS工艺制造的300 MHz, 3.3 V 1 Mb SRAM

1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC Pub Date : 1996-02-08 DOI: 10.1109/ISSCC.1996.488547

H. Pilo, S. Lamphier, F. Towler, R. Hee

引用次数: 11

An adaptive cable equalizer for serial digital video rates to 400 Mb/s 一个自适应电缆均衡器串行数字视频速率为400mb /s

1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC Pub Date : 1996-02-08 DOI: 10.1109/ISSCC.1996.488559

A. Baker

引用次数: 41

Custom ASIC VLSI device for asynchronous transfer mode 自定义ASIC VLSI设备异步传输模式

1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC Pub Date : 1996-02-08 DOI: 10.1109/ISSCC.1996.488532

M. Thomann

{"title":"Custom ASIC VLSI device for asynchronous transfer mode","authors":"M. Thomann","doi":"10.1109/ISSCC.1996.488532","DOIUrl":"https://doi.org/10.1109/ISSCC.1996.488532","url":null,"abstract":"Multiplexing of ATM networks requires flexible switches that efficiently handle data at Gb/s speed. The CellRAM is a single-chip solution implementing a low-cost, low-power ATM multiplexing and switching system. The CellRAM utilizes a shared memory architecture with 8 input and 8 output, double-buffered, serial accessible, memory (SAM) ports and a 4 Mb DRAM memory core. The CellRAM is in a 0.54 /spl mu/m, 3 V double-metal, triple-poly process and is packaged in a 184-pin, quad-flat pack (PQFP). The CellRAM delivers 1.391 Gb/s net ATM cell bandwidth operating at a 43.5 MHz clock rate. Supporting unicast and multicasting functions, the CellRAM has all the necessary features for implementing a switch: input and output queuing, cell routing, cyclic redundancy check (CRC), parity generation and checking, cell address translation, error and status registers, pre- and postpend cell data, multi-configurations, evolutionary memory increase, and an internal refresh counter. This architecture anticipates evolutionary increases in memory density with advances in DRAM technology. The CellRAM 8192 row and 504 column memory core is intended to meet growing memory needs without any change in footprint or specifications.","PeriodicalId":162539,"journal":{"name":"1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129741054","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

A quad-issue out-of-order RISC CPU 一个四问题无序RISC CPU

1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC Pub Date : 1996-02-08 DOI: 10.1109/ISSCC.1996.488574

J. Lotz, S. Naffziger, D. Kipp

引用次数: 23

A 10 Gb/s BiCMOS clock and data recovering 1:4-demultiplexer in a standard plastic package with external VCO 一个10 Gb/s BiCMOS时钟和数据恢复1:4解复用器在一个标准的塑料包装与外部VCO

1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC Pub Date : 1996-02-08 DOI: 10.1109/ISSCC.1996.488571

J. Hauenschild, C. Dorschky, T. von Mohrenfels, R. Seitz

{"title":"A 10 Gb/s BiCMOS clock and data recovering 1:4-demultiplexer in a standard plastic package with external VCO","authors":"J. Hauenschild, C. Dorschky, T. von Mohrenfels, R. Seitz","doi":"10.1109/ISSCC.1996.488571","DOIUrl":"https://doi.org/10.1109/ISSCC.1996.488571","url":null,"abstract":"A test chip for a prototype transmission link performs the task of clock and data recovery together with demultiplexing from 10 to 2.5 Gb/s. The chip uses a BiCMOS process that features a set of devices for high-frequency mixed-signal designs; including 24 GHz NPNs, 0.7 /spl mu/m L/sub eff/ CMOS, 250 and 2000 /spl Omega//sq. polyresistors, 2 fF//spl mu/m/sup 2/ capacitors, Schottky diodes, and lateral PNPs. Early process samples with 16 GHz f/sub T/ are used in the evaluation. Improved performance is expected with the final process. The gates are designed for sufficient speed and nominal VEE of -3.3 V. Even though differential current mode logic (CML) with a differential voltage swing of less than 360 mV/sub pp/ is employed, a wiring capacitance of several 10 fF increases the power-delay product significantly. Wiring length is minimized by local biasing and omission of routing channels. The size of gates with two-level series gating (latch, and, xor) including emitter follower outputs is 67/spl times/58 /spl mu/m/sup 2/. The result of this local biasing scheme is a favourable positive temperature coefficient (TC) for the logic swing, partly compensating for the negative TC of the current switch gain at the cost of high sensitivity to supply variations. All transistors have 0.7 /spl mu/m minimum emitter length, the width avoids the high current region. The other logic gates are downscaled in case of 2.5 GHz operation, input emitter followers omitted in those latches driven from the external clocks.","PeriodicalId":162539,"journal":{"name":"1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128997296","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 12

Fully-integrated 5 V CMOS system for a 20 M sample/s sampling oscilloscope 完全集成的5 V CMOS系统，用于20m采样/s采样示波器

1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC Pub Date : 1996-02-08 DOI: 10.1109/ISSCC.1996.488727

M. Krauss, H. Thieme, H.-G. Schniek, E. Wittig

引用次数: 4

A 100 MHz, 0.4 W RISC processor with 200 MHz multiply adder, using pulse-register technique 一个100mhz, 0.4 W的RISC处理器与200mhz乘加法器，使用脉冲寄存器技术

1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC Pub Date : 1996-02-08 DOI: 10.1109/ISSCC.1996.488544

S. Kozu, M. Daito, Y. Sugiyama, H. Suzuki, H. Morita, M. Nomura, K. Nadehara, S. Ishibuchi, M. Tokuda, T. Nakayama, H. Harigai, Y. Yano

引用次数: 36

Flow-through latch and edge-triggered flip-flop hybrid elements 流动锁存器和边缘触发触发器混合元件

1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC Pub Date : 1996-02-08 DOI: 10.1109/ISSCC.1996.488543

H. Partovi, R. Burd, Udin Salim, F. Weber, Luigi DiGregorio, D. Draper

引用次数: 421

Baseband filters for IS-95 CDMA receiver applications featuring digital automatic frequency tuning 基带滤波器IS-95 CDMA接收机应用，具有数字自动频率调谐

1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC Pub Date : 1996-02-08 DOI: 10.1109/ISSCC.1996.488558

M. Tarsia, Nam, Woo

引用次数: 69