Custom ASIC VLSI device for asynchronous transfer mode

Abstract

Multiplexing of ATM networks requires flexible switches that efficiently handle data at Gb/s speed. The CellRAM is a single-chip solution implementing a low-cost, low-power ATM multiplexing and switching system. The CellRAM utilizes a shared memory architecture with 8 input and 8 output, double-buffered, serial accessible, memory (SAM) ports and a 4 Mb DRAM memory core. The CellRAM is in a 0.54 /spl mu/m, 3 V double-metal, triple-poly process and is packaged in a 184-pin, quad-flat pack (PQFP). The CellRAM delivers 1.391 Gb/s net ATM cell bandwidth operating at a 43.5 MHz clock rate. Supporting unicast and multicasting functions, the CellRAM has all the necessary features for implementing a switch: input and output queuing, cell routing, cyclic redundancy check (CRC), parity generation and checking, cell address translation, error and status registers, pre- and postpend cell data, multi-configurations, evolutionary memory increase, and an internal refresh counter. This architecture anticipates evolutionary increases in memory density with advances in DRAM technology. The CellRAM 8192 row and 504 column memory core is intended to meet growing memory needs without any change in footprint or specifications.