流动锁存器和边缘触发触发器混合元件

1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC Pub Date : 1996-02-08 DOI:10.1109/ISSCC.1996.488543

H. Partovi, R. Burd, Udin Salim, F. Weber, Luigi DiGregorio, D. Draper

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引用次数: 421

摘要

本文描述了一种混合锁存触发器(HLFF)定时方法，旨在大幅降低锁存延迟和时钟负载。采用一个共同的原理来推导静态逻辑、动态多米诺和自复位逻辑的一致闭锁结构。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Flow-through latch and edge-triggered flip-flop hybrid elements

This paper describes a hybrid latch-flipflop (HLFF) timing methodology aimed at a substantial reduction in latch latency and clock load. A common principle is employed to derive consistent latching structures for static logic, dynamic domino and self-resetting logic.

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来源期刊

1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC

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