{"title":"A quad-issue out-of-order RISC CPU","authors":"J. Lotz, S. Naffziger, D. Kipp","doi":"10.1109/ISSCC.1996.488574","DOIUrl":null,"url":null,"abstract":"A 64 b 4-way superscalar PA-RISC microprocessor system operating from 150-250 MHz combines full out-of-order execution with low-cycle time, to produce >360 specint and >550 specfp. Specialized latching and clock circuits and extensive use of dynamic logic enable high frequency operation. 3.8 M logic transistors are integrated on a 17.68/spl times/19.1 mm/sup 2/ die in 3.3 V 0.5 /spl mu/m CMOS.","PeriodicalId":162539,"journal":{"name":"1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC","volume":"69 6","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1996-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"23","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.1996.488574","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 23
Abstract
A 64 b 4-way superscalar PA-RISC microprocessor system operating from 150-250 MHz combines full out-of-order execution with low-cycle time, to produce >360 specint and >550 specfp. Specialized latching and clock circuits and extensive use of dynamic logic enable high frequency operation. 3.8 M logic transistors are integrated on a 17.68/spl times/19.1 mm/sup 2/ die in 3.3 V 0.5 /spl mu/m CMOS.