一个100mhz, 0.4 W的RISC处理器与200mhz乘加法器，使用脉冲寄存器技术

1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC Pub Date : 1996-02-08 DOI:10.1109/ISSCC.1996.488544

S. Kozu, M. Daito, Y. Sugiyama, H. Suzuki, H. Morita, M. Nomura, K. Nadehara, S. Ishibuchi, M. Tokuda, T. Nakayama, H. Harigai, Y. Yano

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引用次数: 36

摘要

最近出现的各种多媒体系统要求微处理器具有高性能、低功耗和信号处理能力等特性。本文提出的118MIPS RISC处理器具有信号处理应用中必不可少的乘加器。使用脉冲寄存器和按需时钟分配，实现了100 MHz, 428 mW 32 b RISC处理器和200 MHz乘加器。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A 100 MHz, 0.4 W RISC processor with 200 MHz multiply adder, using pulse-register technique

Recent emergence of various multimedia systems requires microprocessors to have features like high-performance, low power dissipation, and signal processing capabilities altogether. The 118MIPS RISC processor presented in this paper has a multiply-adder which is essential for signal processing applications. Using a pulse register and on-demand clock distribution, a 100 MHz, 428 mW 32 b RISC processor with 200 MHz multiply-adder is achieved.

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来源期刊

1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC

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